A Polarity-Driven Radiation-Hardened Latch design for Single Event Upset Tolerance

Abstract

The ability of tolerating a radiation-induced single event upset (SEU) is required for nanoscale latches in most dependable applications. This is becoming a strict requirement, because an SEU in a latch node may corrupt its outcome and then, possibly cause a system failure. Moreover, the impact of an SEU further deteriorates for latch designs at reduced CMOS nano-scaled technology because it can result in double node upset (DNU) in addition to single node upset (SNU). Existing approaches of designing a radiation-hardened latch do not achieve complete SNU/DNU tolerance at low hardware overhead. The goal of this paper is to propose a high-performance latch design for SEU tolerance. By exploiting the polarity of the upset in different types of transistors, the proposed design has a small number of sensitive nodes, so incurring in a low protection overhead. Moreover, due to its configuration, the proposed design achieves SEU tolerance at circuit-level without requiring additional layout protection. These advantages make the proposed design superior to all existing hardened latches found in the technical literature; simulation results using 65 nm CMOS technology show that the proposed design achieves a reduction in the range of 14.53% to 98.76% in hardware overhead while providing a complete SNU/DNU recovery.