Design and verification of multiple SEU mitigated circuits on SRAM-based FPGA system

Abstract

This paper addresses the issue of soft error mitigation for Static Random-Access Memory (SRAM)-based Field Programmable Gate Arrays (FPGAs) system in radiation environment to reduce their malfunction and system failure rates in space missions. Seven representative circuits are designed by using the logical resources of SRAM-based FPGA. The accelerator tests investigate that the clock distribution of the Triple Modular Redundancy (TMR) circuits is vital to achieve a high Single Event Upset (SEU) tolerance. The separated DTMR_NEW circuits are proposed to overcome the weakness of the conventional TMR circuits, and a 25× improvement of SEU tolerance for the separated DTMR_NEW circuits are verified. The statistical estimations are desirable for engineers to assess and enhance the SEU tolerance of their designed systems at earlier stages to reduce the time and development costs.