Latch Design Research Articles

Design of a Highly Robust Triple-Node-Upset Self-Recoverable Latch

Due to semiconductor technology scaling, integrated circuits have become more sensitive to soft errors. To effectively tolerate multi-node-upsets caused by soft errors and reduce the power dissipation and delay of a latch, this paper proposes a novel triple-node-upset (TNU) self-recoverable latch design, namely, a highly robust TNU self-recoverable (HTNURE) latch, with many redundant nodes and cyclic storage based on 32-nm CMOS technology. The proposed latch uses the Muller C-element as a basic module and can recover all nodes after a TNU occurs. It has low power dissipation and delay due to the application of clock gating technology and high-speed transmission path technology. The proposed latch design was verified by simulations, and simulation results validate its advantages of low power and delay, and high robustness. In addition, compared with the state-of-the-art TNU-tolerant latches, the proposed latch reduces power dissipation, transmission delay, and power-delay-product by approximately 52%, 25%, and 34%, respectively, with a roughly 17% increase in the number of transistors. Furthermore, the proposed latch is the most cost-effective compared with the TNU-self-recoverable latches, and has less or equivalent sensitivity to the process, voltage, and temperature variation compared with the reference latches.

A Novel Cross-Latch Shift Register Scheme for Low Power Applications

The conventional shift register consists of master and slave (MS) latches with each latch receiving the data from the previous stage. Therefore, the same data are stored in two latches separately. It leads to consuming more electrical power and occupying more layout area, which is not satisfactory to most circuit designers. To solve this issue, a novel cross-latch shift register (CLSR) scheme is proposed. It significantly reduced the number of transistors needed for a 256-bit shifter register by 48.33% as compared with the conventional MS latch design. To further verify its functions, this CLSR was implemented by using TSMC 40 nm CMOS process standard technology. The simulation results reveal that the proposed CLSR reduced the average power consumption by 36%, cut the leakage power by 60.53%, and eliminated layout area by 34.76% at a supply voltage of 0.9 V with an operating frequency of 250 MHz, as compared with the MS latch.

Novel Quadruple-Node-Upset-Tolerant Latch Designs With Optimized Overhead for Reliable Computing in Harsh Radiation Environments

With the rapid advancement of CMOS technologies, nano-scale CMOS latches have become increasingly sensitive to multiple-node upset (MNU) errors caused by radiations. First, this paper proposes a novel latch design, namely QNUTL that can completely tolerate MNUs such as double-node upsets, triple-node upsets (TNUs), and even quadruple-node upsets (QNUs). The latch is mainly constructed from three dual-interlocked-storage-cells (DICEs) and a triple-level soft-error interceptive module (SIM) that consists of six 2-input C-elements. Due to the single-node-upset self-recoverability of DICEs and the soft-error interception of the SIM, the latch can completely tolerate any QNU. Next, by replacing the DICEs in the QNUTL latch by clock-gating (CG) based ones, a QNUTL-CG latch is proposed to significantly reduce power consumption. Simulation results demonstrate the MNU-tolerance of the proposed latches. Moreover, owing to the use of a high-speed transmission path, clock-gating, and a few transistors, the proposed QNUTL-CG latch has low overhead in terms of area, D-Q delay, CLK-Q delay, and setup time, compared with the state-of-the-art TNU-tolerant latch (TNUTL) which is not QNU-tolerant.

Quantum-dot Cellular Automata Latches for Reversible Logic Using Wave Clocking Scheme

The quantum-dot cellular automata computing paradigm shows particular promise in terms of density and power and also enabling a new approach to implement reversible computing. In this paper, we explore the efficient designs of various latches based on reversible logic for quantum-dot cellular automata building blocks, while applying the cell placement constraints introduced by the use of wave clock. Compared to previous literature, the proposed solutions show smaller cell count while using a potentially implementable clocking scheme for molecular QCA wave clocking. The functional correctness of the proposed latches are presented and verified using QCADesigner and HDLQ. Furthermore, we present detailed characterization and analysis, considering different cost metrics of the proposed latches. It is shown that, compared to previous literature, critical paths are decreased by 50%, 33%, 50%, 25% respectively for D-Latch, T-Latch, JK-Latch, and SR latch. There is also an improvement in timing is about 50% for D-Latch and JK-Latch, and 25% for SR-Latch.

High‐performance and single event double‐upset‐immune latch design

This Letter proposes a single event double-upset (SEDU)-fully-tolerant latch, referred to as FBSET, mainly featuring four interlocked branch circuits implemented by stacking three PMOS and one NMOS transistors or three NMOS and one PMOS transistors to achieve low power dissipation. The latch exhibits up to 84.56% area-power-delay product saving compared with recently reported latches. Simulation results validate that the proposed latch is completely immune to SEDU.

Radiation Hardened Latch Designs for Double and Triple Node Upsets

As the process feature size continues to scale down, the susceptibility of logic circuits to radiation induced error has increased. This trend has led to the increase in sensitivity of circuits to multi-node upsets. Previously, work has been done to harden latches against single event upsets (SEU). Currently, there has been a concerted effort to design latches that are tolerant to double node upsets (DNU) and triple node upsets (TNU). In this paper, we first propose a novel DNU tolerant latch design. The latch is designed specifically to provide additional reliability when clock gating is used. Through experimentation, it is shown that the DNU tolerant latch is 11.3 percent more power efficient than existing latch designs suited for clock gating. In addition to the DNU tolerant design, we propose the first TNU tolerant latch. The TNU tolerant latch is shown to provide superior soft error resiliency while incurring a 40 percent overhead compared to DNU tolerant designs.

Design and Evaluation of Low-Complexity Radiation Hardened CMOS Latch for Double-Node Upset Tolerance

Double-node upsets induced by the charge sharing effects are emerging as a major reliability issue in nanometer latch design. Although the existing robust latches can provide a good tolerance for double-node upsets, the implementation of these hardened latches incurs in considerable hardware penalties in terms of delay, area, and power, because they rely on traditional hardening techniques such as space redundancy. In this paper, a novel low-complexity (with respect to hardware redundancy in terms of area, delay, and power) radiation hardened (RH) latch is proposed; this latch is based on the dual interlocked storage cell (DICE). Based on the radiation upset mechanism, in particular the upset polarity of the transient pulse, the proposed RH latch can effectively reduce the number of protected nodes (sensitive nodes), as well as the number of transistors, thus reducing circuit overhead. At the same, a single node upset in any sensitive node and a double-node upset in any sensitive node pair can be recovered, because at least two stable nodes can retain the values even when a double-node upset occurs. The results are based on mapping designs to TSMC 65 nm commercial CMOS process design kit (PDK) and demonstrate that the proposed RH latch incurs in significant reductions in terms of propagation delay, circuit area, and power-delay-area product (PDAP), compared with existing hardened latches. The tolerance functionality of the proposed latch is successfully validated by fault injection. In addition, the impact of variations and process corners is assessed using Monte Carlo (MC) simulation. The simulation results confirm that the proposed latch can also tolerate all upsets, even under extreme values of process variations.

Design of Double-Upset Recoverable and Transient-Pulse Filterable Latches for Low Power and Low-Orbit Aerospace Applications

To meet the requirements of both high reliability and low power in low-orbit aerospace applications, this article first presents a single-event Double-Upset (SEDU) self-Recoverable and single-event Transient (SET) Pulse Filterable (DURTPF) latch design with low power. The DURTPF latch mainly consists of eight mutually feeding-back C-elements (CEs) and an SET pulse filterable Schmitt-trigger (ST). To make an ST behave not only as a pulse filterable ST but also as an error interceptive CE, an input-split ST is created, leading to an enhanced-version of the DURTPF latch, namely DURTPF-EV. The DURTPF-EV latch mainly consists of seven mutually feeding-back CEs including an input-split ST. Simulation results demonstrate both the SEDU self-recoverability and SET pulse filterability of the proposed latches at the cost of moderate silicon area. Using the clock gating technology, the DURTPF latch reduces power dissipation by about 63% on average compared with the state-of-the-art SEDU self-recoverable latch designs that are not SET-pulse filterable. Moreover, the DURTPF-EV latch is more cost-effective and its reliability is also enhanced, making it more suitable for low power and low-orbit aerospace applications.

Design of Robust Latch for Multiple-Node Upset (MNU) Mitigation in Nanoscale CMOS Technology

Multiple-node upsets (MNUs) caused by charge sharing effects are dramatically increasing in advanced nanoscale digital latches. Consequently, the robust latches against MNU cases are increasingly important. Although some existing robust latches are designed to recover MNU cases, they incur significant hardware redundancy and more sensitive nodes due to only depending on multiple circuit instances (e.g., C-elements (CEs)). In order to obtain a balance between high tolerance capability and low overheads, in this paper, we propose a novel radiation hardened latch (RHL) based on the polarity of the radiation-induced voltage pulse (positive or negative pulse). The proposed latch is capable of tolerating any possible single node upset (SNU) and MNU cases in all considered nodes while manifesting fewer transistors and sensitive nodes. The timing (transparent and hold) function and reliability are successfully verified by simulation in TSMC 65nm bulk CMOS process. In addition, the results of the cost comparison have illustrated that the proposed RHL latch has a moderate area and power dissipation, but provides significant benefit in terms of both delay and power-delay-area-product (PDAP) among the alternative latches.

Self-Recovery Tolerance Latch Design Based on the Radiation Mechanism

Digital latches are becoming more sensitive to Multiple-Node Upsets (MNUs) due to lower supply voltage and higher integration density of devices. The hardening technique based on using multiple C-Elements (CEs) (the CE acts as an inverter if its inputs are equal to each other, otherwise holds the high-impedance output) has been used to propose the MNU tolerance latches. However, it brings important hardware overheads. Based on the radiation mechanism, this paper proposes an MNU tolerance latch with self-recovery properties to prevent Singe Node Upset (SNU) and MNU propagation in the feedback loops, and providing the smallest overheads in terms of power, delay, rising time $\text{t}_{\mathrm {r}}$ , falling time $\text{t}_{\mathrm {f}}$ and Power-Delay-Area-Product (PDAP) metric compared with the existing MNU tolerance latches.

Quadruple Cross-Coupled Dual-Interlocked-Storage-Cells-Based Multiple-Node-Upset-Tolerant Latch Designs

First, this paper proposes a double-node-upset (DNU)-completely-tolerant (DNUCT) latch, featuring quadruple cross-coupled dual-interlocked-storage-cells (DICEs) with a C-element. Due to the existence of sufficient feedback loops, the latch can achieve complete DNU toleration. Second, this paper proposes an improved DNUCT latch (referred to as the TNUCT latch) by inserting a redundant level of C-elements at the output stage to intercept node-upset errors accumulated in the upstream DICEs so as to completely tolerate any possible triple-node-upset (TNU). Simulation results demonstrate the robustness of the proposed latches. These innovative latches are also cost-effective due to the use of high-speed transmission paths, clock gating, and fewer transistors. Compared with the typical TNU hardened latch (TNUHL) design that can completely tolerate any TNU, the proposed TNUCT latch reduces the delay-power-area product by approximate 98%. The proposed latches have less or equivalent sensitivity to process, voltage, and temperature variation effects compared with reference latches.

A Novel Low-Cost TMR-Without-Voter Based HIS-Insensitive and MNU-Tolerant Latch Design for Aerospace Applications

With complementary metal oxide semiconductor (CMOS) technology scaling down, radiation induced multiple-node upsets (MNUs) that include double-node-upsets and triple-node upsets (TNUs) are becoming more and more an issue in storage cells used for applications constrained by their environment, such as aerospace applications confronted to radiations. This article presents a novel triple-modular redundancy without voter based high-impedance state (HIS) insensitive and MNU-tolerant latch design, namely TMHIMNT, to ensure both high reliability and low cost. The TMHIMNT latch mainly comprises triple clock-gating (CG) based dual-interlocked-storage-cells (DICEs) and four inverters. Through three internal inverters, the values stored in DICEs converge to a common node feeding an output-level inverter, enabling the TMHIMNT latch to tolerate any possible MNU. Simulation results demonstrate the MNU tolerance of the proposed TMHIMNT latch. Due to the disuse of C-elements, the proposed TMHIMNT latch is insensitive to the HIS, making the latch more reliable for aerospace applications. Moreover, compared with the state-of-the-art TNU hardened latch, due to the use of a high-speed path, CG technologies, and fewer transistors, the proposed TMHIMNT latch can achieve 98% delay, 17% power, and 29% area reductions, respectively.

Information Assurance Through Redundant Design: A Novel TNU Error-Resilient Latch for Harsh Radiation Environment

In nano-scale CMOS technologies, storage cells such as latches are becoming increasingly sensitive to triple-node-upset (TNU) errors caused by harsh radiation effects. In the context of information assurance through redundant design, this article proposes a novel low-cost and TNU on-line self-recoverable latch design which is robust against harsh radiation effects. The latch mainly consists of a series of mutually interlocked 3-input Muller C-elements (CEs) that forms a circular structure. The output of any CE in the latch respectively feeds back to one input of some specified downstream CEs, making the latch completely self-recoverable from any possible TNU, i.e., the latch is completely TNU-resilient. Simulation results demonstrate the complete TNU-resiliency of the proposed latch. In addition, due to the use of fewer transistors and a high-speed path, the proposed latch reduces the delay-power-area product by approximately 91 percent compared with the state-of-the-art TNU hardened latch (TNUHL), which cannot provide a complete TNU-resiliency.

Design of testable reversible latches by using a novel efficient implementation of Fredkin gate

ABSTRACTEnergy dissipation caused by information loss in irreversible computations will be an important limitation for the development of nano-scale circuits in the near future. Reductions in energy dissipation comprise one of the important goals of nanotechnology-based methods, including Quantum dot Cellular Automata (QCA), and so it is desirable to consider reversibility in the design of QCA circuits. In this research, a novel reversible Fredkin gate based on QCA is proposed, which is more efficient and less complex than the conventional Fredkin gate. Conservative reversible logic is parity preserving; hence, any permanent or transient fault can be caused a mismatch between the inputs and the outputs and can be concurrently detected if a reversible circuit is implemented with the conservative Fredkin gate. A single missing/additional cell defect is investigated in the proposed Fredkin gate and fault patterns are presented. To demonstrate the efficiency of the proposed design, some testable reversible sequential elements, such as D-latch, JK-latch, T-latch and SR-latch, are designed by using it. Our proposed concurrent testable designs greatly reduce the occupied area and maximise the circuit density in comparison with previously reported designs. The proposed designs are simulated and verified using QCA Designer ver.2.0.3 and HDLQ.

A Single Event Upset Resilient Latch Design with Single Node Upset Immunity

In this paper, a latch design with single node immunity to single event upsets during the hold state is proposed. This structure is based on the original Quatro latch and have two more redundant storage nodes. Compared with the reference, this structure is able to recover if any of these nodes is struck by ion particles during the hold state and it also has improved multiple node upset performance. Simulations and laser experiment results have validated its effectiveness of SEU resilience by having a larger laser energy threshold for upset and lower SEU error counts compared with the reference. The power, area, and delay penalties are 86%, 48%, and 64% respectively; they are as a consequence of six more transistors added to the latch.

Efficient designs of reversible latches with low quantum cost

Reversible computing is one of the most promising technologies in the design of low-power digital circuits, optical information processing, quantum computing, DNA computing, digital signal processing, and nanotechnology. The main purpose of the design of reversible circuits is to reduce the energy consumption that occurs due to the loss of input bits in irreversible circuits. A gate/block is reversible if the number of inputs and the number of outputs are equal and there is one-to-one correspondence between them. Latches are considered as one of the most important digital structures that are widely used as building blocks in the design of sequential circuits. Here, eight new reversible blocks are first offered. Then using some of them, several effective designs of reversible D, T, and J-K latches are proposed. The results of the evaluations indicate that the proposed latches are superior in terms of quantum cost (QC) than previous designs. Moreover, they are very close to or better than the best previous designs in terms of criteria such as gate count (GC), constant inputs (CI), and garbage outputs (GO).

Resilient Soft-Error Endurable Latch Design

Errors may occur in the circuit output because of upset in the stored or communicated charge. Such errors are considered as Transient Faults. The Transient Fault (TF) causes the soft error in the circuit output. So, designing of the latches which are unsusceptible to the Transient Faults disregarding the hitting particles energy is proposed in this project. Traditionally the soft-error based VLSI is limited to applications which require high reliability and operated in high radiation environment such as avionics applications, medical equipments, space industry and military applications. However, CMOS technology scales down to nanometre region, VLSI circuits also get affected by soft errors at ground level which features low radiation energy. Here, in this paper, totally three soft error tolerant latch designs are proposed, which includes High Performance, low cost and resilient soft error endurable latch, HLR-CG, HLR-CG1 and modified HLR-CG1. The proposed designs achieve better reliability with lower power consumption, delay, power delay product and area. The latches proposed are implemented in 45 nm technology and 32 nm technologies.

An improved current mode logic latch for high‐speed applications

SummaryIn this paper, an improved current mode logic (CML) latch design is proposed for high‐speed on‐chip applications. Transceivers use various methods in fast data transmission in wireless/wire‐line application. For an asynchronous transceiver, the improved CML latch is designed using additional NMOS transistors in conventional CML latch which helps to boost the output voltage swing. The proposed low‐power CML latch‐based frequency divider is compatible for higher operating frequency (16 GHz). Next, the delay model is also developed based on small signal equivalent circuit for the analysis of the proposed latch. The output voltage behavior of the proposed latch is analyzed using 180‐nm standard CMOS technology.

Design of a Triple-Node-Upset Self-Recoverable Latch for Aerospace Applications in Harsh Radiation Environments

In harsh radiation environments, nanoscale CMOS latches have become more and more vulnerable to triple-node upsets (TNUs). This paper first proposes a latch design that can self-recover from any possible TNU for aerospace applications in the 16-nm CMOS technology. The proposed latch is mainly constructed from seven mutually feeding-back soft-error-interceptive modules (SIMs), any of which consists of two three-input C-elements and one two-input C-element. Due to the mutual feedback mechanism of SIMs and the dual-level soft-error interception of each SIM, the latch can self-recover from any possible TNU. Simulation results demonstrate the TNU self-recoverability from any key TNU for the proposed latch using redundant silicon area. Furthermore, using a high-speed path, the proposed latch saves about 95.45% transmission delay and 86.97% delay-power-area product, compared with the state-of-the-art TNU-tolerant latch that cannot provide complete TNU self-recoverability at all.

전통 빗장과 자물쇠를 활용한 스카프 디자인 개발

The purpose of this study is to spread information and knowledge regarding the traditional Korean culture, and foster the cultural fashion product with a perception of high added consumer value, by developing a scarf design with the ability to showcase and highlight a conventional lock and latch motif. Methodology for the study was employed with a comprehensive literature review on the characteristics of native designs featuring locks and latches, a preference survey regarding the basic motif designs, and an empirical study for the design. Chiefly, Adobe Illustrator CS 6 was adopted as a tool for use with the design development. The following information are the results of the study. Five types of applications were applied for the basic motif design based on outcome from a preference survey: simply modelled latch in turtle shape, turtle-shaped latch in realistic mode, ㄷ-shaped lock, fish-like lock, and combined mode with hambak lock and swallow latch designs. These images were designed in order that the themes of tradition and modernity could be harmonized into the designs. As to the utilization of color and tone, such were used as an achromatic color theme with a highest preference level, tranquil greyish tone, and a bright vivid tone in the red and blue series. For the scarf pattern design, a total of 30 pattern designs was developed through various constructions such as utilizing the themes of repeat, rotation and reflection with a basic motif. These designs were proposed to the application to a twilly, long scarf and used on a square scarf. This examination found that traditional latch and lock are recognized as part of the cultural heritage, as a theme reflecting the conventional life craft product native to Korea. These themes were recognized as a reflection of goodness in the Korean culture, and the acceptance of the themes shows that there is an unlimited possibility for the developed and continued use of these specific themes as represented in cultural fashion goods, which can also be seen to have a place in Korean culture to show a modern sense of purpose and style for the enjoyment of the Korean people.