Design of a Triple-Node-Upset Self-Recoverable Latch for Aerospace Applications in Harsh Radiation Environments

Abstract

In harsh radiation environments, nanoscale CMOS latches have become more and more vulnerable to triple-node upsets (TNUs). This paper first proposes a latch design that can self-recover from any possible TNU for aerospace applications in the 16-nm CMOS technology. The proposed latch is mainly constructed from seven mutually feeding-back soft-error-interceptive modules (SIMs), any of which consists of two three-input C-elements and one two-input C-element. Due to the mutual feedback mechanism of SIMs and the dual-level soft-error interception of each SIM, the latch can self-recover from any possible TNU. Simulation results demonstrate the TNU self-recoverability from any key TNU for the proposed latch using redundant silicon area. Furthermore, using a high-speed path, the proposed latch saves about 95.45% transmission delay and 86.97% delay-power-area product, compared with the state-of-the-art TNU-tolerant latch that cannot provide complete TNU self-recoverability at all.