Abstract
Digital latches are becoming more sensitive to Multiple-Node Upsets (MNUs) due to lower supply voltage and higher integration density of devices. The hardening technique based on using multiple C-Elements (CEs) (the CE acts as an inverter if its inputs are equal to each other, otherwise holds the high-impedance output) has been used to propose the MNU tolerance latches. However, it brings important hardware overheads. Based on the radiation mechanism, this paper proposes an MNU tolerance latch with self-recovery properties to prevent Singe Node Upset (SNU) and MNU propagation in the feedback loops, and providing the smallest overheads in terms of power, delay, rising time $\text{t}_{\mathrm {r}}$ , falling time $\text{t}_{\mathrm {f}}$ and Power-Delay-Area-Product (PDAP) metric compared with the existing MNU tolerance latches.
Highlights
The scaling trend of nanoscale CMOS process technology is dramatically leading to the reduction of supply voltage and the increase of integration density, making digital latches more susceptible to Multiple-Node Upsets (MNUs) caused by charge sharing [1].Similar to Single Node Upsets (SNUs), MNUs are regarded as nondestructive errors
Because the sequential part of the proposed MNU tolerance (MT) latch is comprised of two identical storage cells, we only focus on the SNU and MNU self-recovery of one cell in the following analysis
This paper uses the polarity of radiation voltage pulse to propose a novel MNU self-recovery latch
Summary
The scaling trend of nanoscale CMOS process technology is dramatically leading to the reduction of supply voltage and the increase of integration density (the proximity of the nodes), making digital latches more susceptible to Multiple-Node Upsets (MNUs) caused by charge sharing [1]. The MNU self-recovery analysis of occurring on two storage cells is as follows (assuming that Q is latching 1): MNU takes place on S1-S5– this MNU can close N2, N9, N8 and N3, and open P8, P9, P16 and P1, while P3, P7, N5, P11, P15 and N11 are on because their deriving nodes maintain the correct values. MNU takes place on S1-S8–N2, N9 and N11 are closed, and P8, P9, P13 and P12 are opened These upset nodes can be restored by P3, P7, N5, P10 and P14 because S2 ∼ S4 and S7 are the correct values. The latches in [5] and [4] use the interlocked CE instances to implement MNU self-recovery tolerance, so they require more devices and nodes, compared with the proposed MT latch.
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