Latch Comparator Research Articles

Charge pump-based PVT-resilient 45 nm CMOS dynamic comparator leveraging high speed and power efficiency

High-speed, low-power consumption, compact area, and high resolution are critical for analog /mixed signal applications. This article presents a novel design for a dynamic latch comparator that achieves exceptional speed, minimal power consumption, and a significantly reduced die area. The innovative comparator leverages a novel charge shared logic-based reset technique, which enables unparalleled speed and power efficiency. Rigorous simulations and analyses confirm that the delay time is drastically reduced compared to traditional dynamic latched comparators. The results clearly indicate that the proposed design exhibits high tolerance to PVT (process, voltage, and temperature) variations, making it highly suitable for mixed-signal applications. Designed and simulated using advanced 45 nm CMOS technology, the proposed circuit achieves an impressive delay of 18.5 ps and a remarkably low power consumption of 3.66 μW at a 1 V supply voltage and 1 GHz clock frequency.

Design and Investigation of the 22 nm FinFET Based Dynamic Latched Comparator for Low Power Applications

Design and Investigation of the 22 nm FinFET Based Dynamic Latched Comparator for Low Power Applications

Ultra-low power magneto-elastic analog-to-digital converter based on magnetic tunnel junctions and bicomponent multiferroic nanomagnet

<sec>In recent years, the utilization of artificial intelligence and big data has led to the rise of compute-in-memory signal processing as the primary method for ADC design. Spintronic memory devices, which have non-volatile and low static power consumption characteristics, are particularly suitable for the design of low-power, high-bandwidth compute-in-memory ADCs.</sec><sec>In this paper, a 3-bit magneto-elastic analog-to-digital converter (MEADC) is proposed, which comprises eight magnetic tunnel junctions (MTJs), where the MTJ free layer is a bicomponent multiferroic nanomagnet. The bicomponent multiferroic nanomagnet can attain deterministic magnetization switching under zero-field condition by regulating the strain-mediated voltage. It has been discovered that there is a linear correlation between the thickness of the piezoelectric layer and the critical flip voltage in a bicomponent multiferroic nanomagnet of a given size and material. Using this principle, the thickness of the piezoelectric layer is adjusted to allow the MEADC to have eight different voltage switching thresholds. This can make the analog signal converted into a combination of different magnetization states of eight multiferroic MTJ. A latch comparator and an independent read circuit are designed to detect the MTJ’s resistance state output a digital signal. Monte Carlo simulations indicate that the MEADC can achieve a 100% success rate of writing at room temperature. Additionally, the read circuit and write circuit are separated from each other, thus the same reference voltage can be set for each MTJ and result in higher readability. Micromagnetic simulation and numerical analysis demonstrate that the MEADC can operate at a maximum frequency of 250 MHz, and the energy consumption of a single conversion is only 20 aJ. Compared with the magnetic analog-to-digital converter based on the Racetrack technology, the energy consumption is reduced by 1000 times, and the sampling rate is increased by 10 times. The MEADC proposed in this paper offers an essential technical support for the spintronics-based compute-in-memory integrated circuit architecture.</sec>

A 103 fJ/b/dB, 10–26 Gb/s Receiver With a Dual Feedback Nested Loop CDR for Wide Bandwidth Jitter Tolerance Enhancement

A 10–26 Gb/s energy-efficient receiver incorporating a dual-feedback nested loop clock and data recovery circuit (DF-CDR) is proposed. Combining a direct modulation path on voltage-controlled oscillator (VCO) and phase interpolator (PI)-based phase rotator inside a phase locked loop (PLL), it improves high-frequency jitter tolerance by 0.15 UI. An edge-first equalization scheme is proposed to reduce power and hardware overhead of decision feedback equalizers. Meanwhile, it facilitates adaptive equalization of continuous time linear equalizer, and background offset calibration of the receiver frontend. A three-stage latch comparator is adopted to enable high-speed direct feedback equalizer. By applying PRBS-31 test pattern through a 32 dB loss channel, the receiver is error-free and features the best energy efficiency of 103 fJ/b/dB at 26 Gb/s.

An Review of Dynamic CMOS Comparators

CMOS dynamic comparators contributes a major role on the implementation of mixed signal successive approximation register (SAR) type of analog to digital converters (ADC). High precision, dynamic range, low voltage operation, high speed, low power consumption, reliability and offset voltage are the critical factors to be considered while designing CMOS dynamic comparators. This paper reviewed the performance of some popular dynamic CMOS comparators such as StrongARM latch comparator, double- tail dynamic-latched comparator, dynamic bias comparator and triple stage somparator.

Review of Four Improving Designs of Dynamic Latch Comparator

In this paper, four disparate designs of dynamic latch comparators are discussed consecutively. By improving the design of the pre-amplifier stage, the double tail comparator provides a good power-speed trade-off. Further, Differential pair amplifiers are implemented in the second design, which has better comparison speed and energy dissipation. Next, a bulk-driven structure is employed on the comparator design to improve the comparison speed. Finally, a dynamic comparator utilizes a floating reservoir capacitor and a positive feedback bulk structure is introduced to achieve higher energy efficiency. The overall performance of these comparators is evaluated in this paper.

A low offset low power CMOS dynamic comparator for analog to digital converters

In this research, a new architecture of dynamic latch comparator is presented, which is able to provide high-speed, consumes low-power and low offset voltage. The proposed comparator has been verified in a design, a 12-Bit SAR ADC(Successive Approximation Register Charge-Redistribution Analog-To-Digital Converter). The comparator consists of two stage pre-amplifier and a StrongLatch. The pre-amplifier adopts an inverter-based input pair and a pair of capacitances in output stage to reduce noise. It is shown by simulation and analysis that the offset voltage is significantly reduced compared to a conventional dynamic latched comparator. The proposed circuit is designed and simulated in 28 nm CMOS technology. The results show that, for the proposed comparator, the speed is 2.37 ns and consumes only 426.6 μW power, at 1.8 V supply voltage and 330 MHz clock frequency. This article presents two kinds of FoM(Figure of Merit) to prove that the comparator has excellent performance.

Design of Low Power Low Offset Dynamic latch Comparator using DTMOS Technique

Analog to Digital converters plays an essential role in signal processing and medical applications. SAR ADC is best suited for biomedical applications because of its low power and medium resolution. Low power dynamic comparators are essentially desired in the design of SAR ADC. In this paper, a low power dynamic type latch comparator is designed which is based on Dynamic Threshold Metal Oxide Semiconductor (DTMOS ) technique to reduce the power dissipation which is achieved by reducing the supply voltage. The circuit has been implemented at the supply voltage of 0.8 V. The simulations for this comparator are carried out in CADENCE SPECTRE using 45nm CMOS technology. The simulation outcomes validate that the designed dynamic latch comparator with DTMOS techniques is 20% more power saving in comparison to the conventional comparator. The total power consumption is as low as 156.18nW which makes it suitable for low-power bio-medical applications.

Design of a low power high-speed dynamic latched comparator in 65- nm CMOS using peaking techniques

Design of a low power high-speed dynamic latched comparator in 65- nm CMOS using peaking techniques

A column-parallel 1-bit ADC with threshold offset reduction technique for single-bit quanta image sensor

This paper presents a column-parallel 1-bit analog-to-digital converter (ADC) with threshold offset reduction technique, which aims to reduce the bit error rate (BER) of single-bit quanta image sensor (QIS). The fixed offset of the differential charge transfer amplifier (DCTA) and the fixed compensation offset of the calibrated dynamic latch (CD-latch) comparator are eliminated by two coupling capacitors. Additionally, an improved 3-stage DCTA with low gain error is designed to further suppress the fixed residual offset of the CD-latch. The proposed circuit is implemented by a 110 nm CMOS process. Post-simulation results show that the proposed 1-bit ADC achieves a threshold offset of 32.6 μV at 4 MSa/s sampling rate and 500 μV quantization threshold. Compared with the conventional structure, the random noise of the proposed 1-bit ADC remains almost unaltered. Meanwhile, its threshold offset is lowered by 153.6 μV, making the model BER and circuit BER of the column-level circuit reduce from 2.42% to 0.21% and 2.29%–0.26%, respectively.

A Review of Comparators Inprovment Design

This paper reviews and analyzes the three proposed new comparators, as a indirection of future works. The first improved design is the pre-amplifier improved comparator that the input of the latch is changed to a PMOS transistor, and a pair of cross-coupled transistors are used in the preamplifier part to amplify the gain, which finally realizes the proposed circuit with better comparison speed, more less power dissipation. The switch separated latch comparator is another improved design that the latching stage with separate gate-biased cross-coupled transistors. Using this new transconductance-enhanced latching stage enables dramatic reductions in delay and power dissipation. The third type of comparator proposed is an innovative design. It adds a capacitor to the input tail current source of the preamplifier. Compared with the original Elzakker comparator, power dissipation has dropped by almost 50%.

An Adiabatic Capacitive Artificial Neuron With RRAM-Based Threshold Detection for Energy-Efficient Neuromorphic Computing

In the quest for low power, bio-inspired computation both memristive and memcapacitive-based Artificial Neural Networks (ANN) have been the subjects of increasing focus for hardware implementation of neuromorphic computing. One step further, regenerative capacitive neural networks, which call for the use of adiabatic computing, offer a tantalising route towards even lower energy consumption, especially when combined with `memimpedace' elements. Here, we present an artificial neuron featuring adiabatic synapse capacitors to produce membrane potentials for the somas of neurons; the latter implemented via dynamic latched comparators augmented with Resistive Random-Access Memory (RRAM) devices. Our initial 4-bit adiabatic capacitive neuron proof-of-concept example shows 90% synaptic energy saving. At 4 synapses/soma we already witness an overall 35% energy reduction. Furthermore, the impact of process and temperature on the 4-bit adiabatic synapse shows a maximum energy variation of 30% at 100 degree Celsius across the corners without any functionality loss. Finally, the efficacy of our adiabatic approach to ANN is tested for 512 & 1024 synapse/neuron for worst and best case synapse loading conditions and variable equalising capacitance's quantifying the expected trade-off between equalisation capacitance and range of optimal power-clock frequencies vs. loading (i.e. the percentage of active synapses).

A Design of 10-Bit Asynchronous SAR ADC with an On-Chip Bandgap Reference Voltage Generator.

A proposed prototype of a 10-bit 1 MS/s single-ended asynchronous Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) with an on-chip bandgap reference voltage generator is fabricated with 130 nm technology. To optimize the power consumption, static, and dynamic performance, several techniques have been proposed. A dual-path bootstrap switch was proposed to increase the linearity sampling. The Voltage Common Mode (VCM)-based Capacitive Digital-to-Analog Converter (CDAC) switching technique was implemented for the CDAC part to alleviate the switching energy problem of the capacitive DAC. The proposed architecture of the two-stage dynamic latch comparator provides high speed and low power consumption. Moreover, to achieve faster bit conversion with an efficient time sequence, asynchronous SAR logic with an internally generated clock is implemented, which avoids the requirement of a high-frequency external clock, as all conversions are carried out in a single clock cycle. The proposed error amplifier-based bandgap reference voltage generator provides a stable reference voltage to the ADC for practical implementation. The measurement results of the proposed SAR ADC, including an on-chip bandgap reference voltage generator, show an Effective Number of Bits (ENOB) of 9.49 bits and Signal-to-Noise and Distortion Ratio (SNDR) of 58.88 dB with 1.2 V of power supply while operating with a sampling rate of 1 MS/s.

Digitally assisted dynamic comparator with reduced offset across process, voltage, and temperature variations

A dynamic latched comparator with a programmable tail transistor is proposed. The tail transistor is divided into N branches that could be enabled or disabled to allow optimizing the delay and offset of the comparator across process, voltage, and temperature variations. As a proof of concept, a 2.5 GHz design example with 4 branches is carried out in a 65 nm CMOS technology. The design utilizes digital calibration circuitry to automatically set the number of enabled branches under given operating conditions, with the goal to minimize the offset while achieving the target speed. Such offset reduction helps in efficiently cancelling the offset with simple overhead circuitry. Simulation results show that the offset and power consumption of the proposed comparator in the fast-fast corner are reduced by 41% and 26% respectively compared to a conventional StrongARM design targeting the same speed.

A High Efficiency Low Noise RF-to-DC Converter Employing Gm-Boosting Envelope Detector and Offset Canceled Latch Comparator

This work presents a high efficiency RF-to-DC conversion circuit composed of an LC-CL balun-based Gm-boosting envelope detector, a low noise baseband amplifier, and an offset canceled latch comparator. It was designed to have high sensitivity with low power consumption for wake-up receiver (WuRx) applications. The proposed envelope detector is based on a fully integrated inductively degenerated common-source amplifier with a series gate inductor. The LC-CL balun circuit is merged with the core of the envelope detector by sharing the on-chip gate and source inductors. The proposed technique doubles the transconductance of the input transistor of the envelope detector without any extra power consumption because the gate and source voltage on the input transistor operates in a differential mode. This results in a higher RF-to-DC conversion gain. In order to improve the sensitivity of the wake-up radio, the DC offset of the latch comparator circuit is canceled by controlling the body bias voltage of a pair of differential input transistors through a binary-weighted current source cell. In addition, the hysteresis characteristic is implemented in order to avoid unstable operation by the large noise at the compared signal. The hysteresis window is programmable by changing the channel width of the latch transistor. The low noise baseband amplifier amplifies the output signal of the envelope detector and transfers it into the comparator circuit with low noise. For the 2.4 GHz WuRx, the proposed envelope detector with no external matching components shows the simulated conversion gain of about 16.79 V/V when the input power is around the sensitivity of −60 dBm, and this is 1.7 times higher than that of the conventional envelope detector with the same current and load. The proposed RF-to-DC conversion circuit (WuRx) achieves a sensitivity of about −65.4 dBm based on 45% to 55% duty, dissipating a power of 22 μW from a 1.2 V supply voltage.

Erratum

IET Circuits, Devices & SystemsVolume 15, Issue 7 p. 695-695 ERRATUMOpen Access Erratum This article corrects the following: A low-offset low-power and high-speed dynamic latch comparator with a preamplifier-enhanced stage Jérôme K. Folla Maria L. Crespo Evariste T. Wembe Mohammad A. S. Bhuiyan Andres Cicuttin Bernard Z. Essimbi Mamun B. I. Reaz Volume 15Issue 1IET Circuits, Devices & Systems pages: 65-77 First Published online: December 17, 2020 First published: 16 April 2021 https://doi.org/10.1049/cds2.12061AboutSectionsPDF ToolsRequest permissionExport citationAdd to favoritesTrack citation ShareShare Give accessShare full text accessShare full-text accessPlease review our Terms and Conditions of Use and check box below to share full-text version of article.I have read and accept the Wiley Online Library Terms and Conditions of UseShareable LinkUse the link below to share a full-text version of this article with your friends and colleagues. Learn more.Copy URL Share a linkShare onEmailFacebookTwitterLinked InRedditWechat https://doi.org/10.1049/cds2.12008 In Folla et al. [1], the following corrections should be noted. Figure 6–12 were changed. REFERENCE 1Folla, J.K., et al.: A low-offset low-power and high-speed dynamic latch comparator with a preamplifier-enhanced stage. IET Circuits Devices Syst. 15(1), 65– 77 (2021). https://doi.org/10.1049/cds2.12008Wiley Online LibraryWeb of Science®Google Scholar Volume15, Issue7October 2021Pages 695-695 ReferencesRelatedInformation

A 9.38-bit, 422nW, high linear SAR-ADC for wireless implantable system

In wireless implantable systems (WIS) low power consumption and linearity are the most prominent performance metrics in data acquisition systems. successive approximation register-analog to digital converter (SAR-ADC) is used for data processing in WIS. In this research work, a 10-bit low power high linear SAR-ADC has been designed for WIS. The proposed SAR-ADC architecture is designed using the sample and hold (S/H) circuit consisting of a bootstrap circuit with a dummy switch. This SAR-ADC has a dynamic latch comparator, a split capacitance digital to analog converter (SC-DAC) with mismatch calibration, and a SAR using D-flipflop. This architecture is designed in 45 nm CMOS technology. This ADC reduces non-linearity errors and improve the output voltage swing due to the usage of a clock booster and dummy switch in the sample and hold. The calculated outcomes of the proposed SAR ADC display that with on-chip calibration an ENOB of 9.38 (bits), spurious free distortion ratio (SFDR) of 58.621 dB, and ± 0.2 LSB DNL and ± 0.4LSB INL after calibration.

Design and Performance of High-Speed Energy-Efficient CMOS Double Tail Dynamic Latch Comparator Using GACOBA Load Suitable for Low Voltage Applications

The need of energy-efficient, high-speed, and low-offset analog-to-digital converters is forcing to design the dynamic latch comparators to enhance the speed and energy efficiency with minimum offset. This paper presents a novel double tail dynamic latch comparator using bulk-driven process and common-gate (CG) amplifier in amplification stage. The gain of amplification stage is enhanced using GACOBA load in which gain is controlled by bulk amplification through CG amplifier. It results in remarkable enhancement in regeneration speed and reduction in power consumption. The analytical expressions of delay and offset due to mismatch are also derived. These derivations explore the key contributors to reduce the delay and offset of proposed comparator. The outcomes are verified in CADENCE SPECTRE at 45-nm CMOS process technology through various simulations and Monte-Carlo analysis at different process corners. The post-layout analysis validates the simulation results. The proposed comparator is 93% more energy-efficient and lessens more than 84% delay in comparison of conventional design. The 1–[Formula: see text] input offset voltage and average input voltage error due to kickback noise are 2.48[Formula: see text]mV and 0.824[Formula: see text][Formula: see text]V, respectively at 0.8[Formula: see text]V power supply with 34.32[Formula: see text][Formula: see text]m2 active area.

Design and Analysis of Dynamic Comparator Implemented Using Stacking Technique

Comparatorsareone of the basic devices that is mostly used in analog-to-digital converters (ADC). Designing low-power circuits with CMOS technology has been a serious research problem for several years. Nowadays the need of low power electronics became vital in various fields. In this paper, stacking technique is used to reduce the power consumed by the comparator.65nm CMOS process is used to design and simulate the comparator. The power consumption ofproposed comparator is compared with thepower consumption of double tail dynamic latch comparator. The proposed approach obtained less power consumption results.

Высокоточный двухступенчатый АЦП с изменяемым диапазоном сравнения с использованием компаратора на основе защелки

Due to the technology development and decreasing supply voltages, undesirable effects on sensitive analog signals like noise, kickback are becoming more expressed. Mentioned issues are present in analog to digital converters (ADC) and design of high accuracy ADCs is becoming more complex. In this work, a circuit was proposed based on a latch comparator and comparison range shifter, which increased the accuracy of a two-step flash ADCs by excluding the chance of incorrect coarse conversion, when the input analog voltage is close to separating points of the comparison range of first stage of the ADC. The proposed circuit was constructed using an 16nm FinFET process, the simulations were done with HSpice simulator. The idea was to increase the accuracy of an already designed two-step flash ADC by adding the proposed circuit, which was done by shifting the comparison range during the coarse conversion, for the difference of input voltage and separating points not to be smaller than the offset of comparators used in ADC. It was established that the use of the proposed circuit increased the comparison time, as the sampled input analog voltage firstly should be compared with comparison range separating points, but on the other hand the ADC became more sensitive to its input change (up to 4mV offset) and was performing stable, excluding the chance of wrong coarse conversion. It has been shown that proposed architecture allows avoiding the use of low offset and high accuracy complex comparators in two-step flash ADCs, which greatly reduces the layout area.