Design of Low Power Low Offset Dynamic latch Comparator using DTMOS Technique

Abstract

Analog to Digital converters plays an essential role in signal processing and medical applications. SAR ADC is best suited for biomedical applications because of its low power and medium resolution. Low power dynamic comparators are essentially desired in the design of SAR ADC. In this paper, a low power dynamic type latch comparator is designed which is based on Dynamic Threshold Metal Oxide Semiconductor (DTMOS ) technique to reduce the power dissipation which is achieved by reducing the supply voltage. The circuit has been implemented at the supply voltage of 0.8 V. The simulations for this comparator are carried out in CADENCE SPECTRE using 45nm CMOS technology. The simulation outcomes validate that the designed dynamic latch comparator with DTMOS techniques is 20% more power saving in comparison to the conventional comparator. The total power consumption is as low as 156.18nW which makes it suitable for low-power bio-medical applications.