Design and Analysis of Dynamic Comparator Implemented Using Stacking Technique

Abstract

Comparatorsareone of the basic devices that is mostly used in analog-to-digital converters (ADC). Designing low-power circuits with CMOS technology has been a serious research problem for several years. Nowadays the need of low power electronics became vital in various fields. In this paper, stacking technique is used to reduce the power consumed by the comparator.65nm CMOS process is used to design and simulate the comparator. The power consumption ofproposed comparator is compared with thepower consumption of double tail dynamic latch comparator. The proposed approach obtained less power consumption results.