Digitally assisted dynamic comparator with reduced offset across process, voltage, and temperature variations

Abstract

A dynamic latched comparator with a programmable tail transistor is proposed. The tail transistor is divided into N branches that could be enabled or disabled to allow optimizing the delay and offset of the comparator across process, voltage, and temperature variations. As a proof of concept, a 2.5 GHz design example with 4 branches is carried out in a 65 nm CMOS technology. The design utilizes digital calibration circuitry to automatically set the number of enabled branches under given operating conditions, with the goal to minimize the offset while achieving the target speed. Such offset reduction helps in efficiently cancelling the offset with simple overhead circuitry. Simulation results show that the offset and power consumption of the proposed comparator in the fast-fast corner are reduced by 41% and 26% respectively compared to a conventional StrongARM design targeting the same speed.