Abstract
IET Circuits, Devices & SystemsVolume 15, Issue 7 p. 695-695 ERRATUMOpen Access Erratum This article corrects the following: A low-offset low-power and high-speed dynamic latch comparator with a preamplifier-enhanced stage Jérôme K. Folla Maria L. Crespo Evariste T. Wembe Mohammad A. S. Bhuiyan Andres Cicuttin Bernard Z. Essimbi Mamun B. I. Reaz Volume 15Issue 1IET Circuits, Devices & Systems pages: 65-77 First Published online: December 17, 2020 First published: 16 April 2021 https://doi.org/10.1049/cds2.12061AboutSectionsPDF ToolsRequest permissionExport citationAdd to favoritesTrack citation ShareShare Give accessShare full text accessShare full-text accessPlease review our Terms and Conditions of Use and check box below to share full-text version of article.I have read and accept the Wiley Online Library Terms and Conditions of UseShareable LinkUse the link below to share a full-text version of this article with your friends and colleagues. Learn more.Copy URL Share a linkShare onEmailFacebookTwitterLinked InRedditWechat https://doi.org/10.1049/cds2.12008 In Folla et al. [1], the following corrections should be noted. Figure 6–12 were changed. REFERENCE 1Folla, J.K., et al.: A low-offset low-power and high-speed dynamic latch comparator with a preamplifier-enhanced stage. IET Circuits Devices Syst. 15(1), 65– 77 (2021). https://doi.org/10.1049/cds2.12008Wiley Online LibraryWeb of Science®Google Scholar Volume15, Issue7October 2021Pages 695-695 ReferencesRelatedInformation
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