High-speed and low-power dynamic latch comparator

Abstract

This paper presents the comparison between the CMOS dynamic latch comparators. High speed and low power comparators are essential building blocks of high speed analog to digital converters (ADCs). The comparator circuit take for study are dynamic latch comparator using preamplifier and dynamic latch with inverter buffer. Preamplifier dynamic latch circuit that consists of a preamplifier followed by a double regenerative dynamic latch, this preamplifier uses fully differential circuit which decreases the effects of offset voltage error due to device mismatch. Buffered dynamic latch circuit includes a basic dynamic latch comparator followed by an inverter buffer stage. The inverter buffers are added to isolate the comparator output and large node capacitance also used to minimize the offset errors. The circuit using SPICE tool with 0.18um technology and the supply voltage used 1.8V.