CMOS Charge-transfer Preamplifier For Offset-fluctuation In Low-power, High-accuracy Comparators

Abstract

We have developed a low-power and high-accuracy comparator composed of a dynamic latch and a CMOS charge transfer preamplifier (CT preamp). The CT preamp amplifies the input signal with no dc power dissipation and the operation is almost insensitive to the device parameter fluctuations in the preamp. The fluctuation in the offset voltage of a dynamic latch is reduced by a factor of the preamp gain. The circuit operation has been verified by measurements on test circuits fabricated by 0.6 pm CMOS process. Introduction Low power operation of analog-to-digital converters (ADC) is becoming increasingly important in portable applications. For this purpose, we have proposed a low- power two-step ADC circuitry which consists of a capacitive dividing reference voltage generator and dynamic latch comparators (l). It operates in a purely dynamic mode, resulting in very low power consumption. However, a dynamic latch has large fluctuation in the offset voltage (several tens mV) due to the threshold-voltage mismatch of pair transistors in the difference amplifier circuit. Therefore, the new ADC architecture is not applicable to video signal application which requires 8-10 bit resolution (2-8 mV accuracy for comparators). In order to solve the problem of large offset-voltage fluctuation in a dynamic latch circuitry, we have introduced a CMOS charge-transfer preamplifier (CT preamp) in front of a dynamic latch. The CT preamp is insensitive to the device parameter fluctuations and amplifies the input signal with no dc power dissipation, resulting in realization of a high- accuracy and low-power comparator. In this paper, we present a circuit operation of the CMOS CT preamp and the effectiveness of the circuit is demonstrated by the HSPICE simulation results and the measurement results of fabricated test circuits. CMOS Charge Transfer Preamplifier Fig. 1 shows the circuit diagram and the operation of the CMOS CT preamp. Capacitance(CT)-loaded nMOS and PMOS share the common drain electrode and the common gate electrode. The common drain forms the output of the CT preamp which is fed to the dynamic latch circuit. The gate electrode is capacitively coupled to VIN or VREF (comparator inputs). The capacitance CO corresponds to the input capacitance of the dynamic latch. The circuit operates in three cycles. In the first cycle, the two capacitors (CT) are discharged by shorting the electrodes. In the second cycle, the two capacitors (CT) are charged through the source follower action of PMOS and nMOS transistors whose gate electrodes are biased to VPR. The charging automatically stops when the gate-source voltages of the PMOS and the nMOS reach the threshold voltages, VTP and VTN, respectively. As a result, the two capacitors are precharged to VpR-VTp and VPR- VTN. Then, in the third cycle, the common drain is made floating and the comparator input is switched from VIN to VWF. The charge redistribution occurs between CO and CT through the source follower action of either the nMOS or VPH ? 9 rl C