Large Test Data Volume Research Articles

Robust Anomaly Detection for Multivariate Data of Spacecraft Through Recurrent Neural Networks and Extreme Value Theory

Spacecraft anomaly detection which could find anomalies in the telemetry or test data in advance and avoid the occurrence of catastrophic failures after taking corresponding measures has elicited the attention of researchers both in academia and aerospace industry. Current spacecraft anomaly detection systems require costly knowledge and human expertise to identify a true anomaly. Moreover, some new problems and challenges such as large volume of test data, imbalanced data distribution and the scarcity of faulty labeled samples have emerged. In this work, we propose an unsupervised anomaly detection algorithm combining Gated Recurrent Unit (GRU) based Recurrent Neural Network (RNN) and Extreme Value Theory (EVT). First, we develop a two-layer ensemble learning based predictor framework which stacks three GRU-based networks with different architectures to learn and capture the normal behavior of multiple channels of data. Then, the prediction errors are calculated and smoothed using Exponentially Weighted Moving Average (EWMA) algorithm. Next, we propose a detection rule setting anomaly threshold automatically through EVT which does not assume any parent distribution on the prediction errors. To the best of our knowledge, it is the first attempt that stacked GRU-based predictors with EVT has been employed into the spacecraft anomaly detection. Through extensive experiments conducted on public datasets as well as real data sampled from a launch vehicle, we show that the proposed detection algorithm is superior to other state-of-the-art anomaly detection approaches in terms of model performance and robustness.

Thermal-aware Test Data Compression for System-on-Chip Based on Modified Bitmask Based Methods

High temperature during test mode and the large volume of test data are the two prominent challenges in the testing of System-on-Chip (SoC). Temperature relies on the spatial power distribution between the blocks of the chip. An efficient don’t care filling technique is proposed to minimize the non-uniform spatial power distribution, which, in turn, reduces the peak temperature of the chip. However, high test data compression can be obtained by carefully mapping the don’t care bits to get more similar subvectors in the precomputed test patterns. The don’t care bits in the given test set can be utilized for test data compression and peak temperature reduction. As the same don’t care bits are to be used for both peak temperature reduction and test data compression, the two techniques conflict with each other. An integrated approach is presented to keep peak temperature under the safe limit with low test compression loss. Experimental results on ISCAS’89 benchmark circuits demonstrate the effectiveness of the proposed approach

A variable-length compatible compression scheme based on tristate signals

The test data volume for the manufacturing test of chips is increasing rapidly. This is due to the fact that the complexity of these chips is increasing rapidly and the transistor count is increasing exponentially. Aimed at solving the problems of large test data volume and long test time in chips test, this paper presents a deterministic test-based compression method that uses tristate signals encoding and compatible test cube merging. Firstly, the partial input reduction is carried out for the original test set. The proportion of “don’t care” bits in the original test set is increased by merging compatible or inversely compatible inputs in the test cubes, so the compatibility among the test cubes is improved. Then, the test set is compressed and encoded by using tristate signal. Each test cube is divided into several data segments, which are encoded by tristate signals and multiple compatibility rules. This scheme can improve the compression ratio of the test set. The experimental results show that the proposed scheme achieves a good compression ratio, without excessive test power and area overhead. The average test compression ratio can reach 82.15%.

A SoC-IP Core Test Data Compression Scheme based on Error Correcting Hamming Codes

As system-on-chip (SoC) integration is growing very rapidly, increased circuit densities in SoC have lead a radical increase in test data volume and reduction of this large test data volume is one of the biggest challenges in the testing industry. This paper presents an efficient test independent compression scheme primarily based on the error correcting Hamming codes. The scheme operates on the pre-computed test data without the need of structural information of the circuit under test and thus it is applicable for IP cores in SoC. Test vectors are equally sliced into the size of ‘<em>n’</em> bits. Individual slices are treated as a Hamming codeword consisting of ‘<em>p’</em> parity bits and ‘<em>d’</em> data bits (<em>n = d + p)</em> and validity of each codeword is verified. If a valid slice is encountered<em>’</em> data bits prefixed by ‘<em>1’</em> are written to the compressed file, while for a non-valid slice all ‘<em>n’</em> bits preceded by ‘<em>0’</em> are written to the compressed file. Finally, we apply Huffman coding and RLE in order to improve the compression ratio further The efficiency of the proposed hybrid scheme is verified with the experimental outcomes and comparisons to existing compression methods suitable for testing of IP cores.

Testing 3D-SoCs Using 2-D Time-Division Multiplexing

Through-silicon vias (TSVs) are used as high-speed vertical interconnects between dies in a 3-D system-on-a-chip (SoC). However, their speed cannot be exploited during test application due to inherent limitations of the scan-chains of the cores, which prevent the use of high shift frequencies during the scan-in/out operations. Moreover, due to their high area cost, only a limited number of TSVs can be utilized for test application. As a result, TSVs become the bottleneck for transferring the large volume of test-data to the various layers of the stack, and the time for testing the 3-D chip increases a lot. In this paper, we propose an efficient test-access mechanism (TAM) architecture that exploits the high speed of TSVs to minimize the time for testing 3-D SoCs. The proposed TAM architecture is based on a 2-D time-division-multiplexing approach, and by the means of a very effective test-scheduling method, it offers significant savings in test-time, TSV-count and TAM-cost under power and thermal constraints. Extensive experiments on two 3-D benchmark SoCs show the benefits of the proposed method.

Enhancing the performance of distributed big data processing systems using Hadoop and Polybase

The approach to improvement of performance of distributed information systems based on sharing technologies of the Hadoop cluster and component of SQL Server PolyBase was considered. It was shown that the relevance of the problem, solved in the research, relates to the need for processing Big Data with different way of representation, in accordance with solving diverse problems of business projects. An analysis of methods and technologies of creation of hybrid data warehouses based on different data of SQL and NoSQL types was performed. It was shown that at present, the most common is the technology of Big Data processing with the use of Hadoop distributed computation environment. The existing technologies of organization and access to the data in the Hadoop cluster with SQL-like DBMS by using connectors were analyzed. The comparative quantitative estimates of using Hive and Sqoop connectors during exporting data to the Hadoop warehouse were presented. An analysis of special features of Big Data processing in the architecture of Hadoop-based distributed cluster computations was carried out. The features of Polybase technology as a component of SQL Server for organizing a bridge between SQL Server and Hadoop data of the SQL and NoSQL types were presented and described. The composition of the model computer plant based on the virtual machine for implementation of joint setting of PolyBase and Hadoop for solving test tasks was described. A methodological toolset for the installation and configuration of Hadoop and PolyBase SQL Server software was developed with consideration of constraints on computing capacities. Queries for using PolyBase and data warehouse Hadoop when processing Big Data were considered. To assess the performance of the system, absolute and relative metrics were proposed. For large volume of test data, the results of the experiments were presented and analyzed, which illustrated an increase in productivity of the distributed information system – query execution time and magnitude of memory capacity of temporary tables, created in this case. A comparative analysis of the studied technology with existing connectors with Hadoop cluster, which showed the advantage of PolyBase over connectors of Sqoop and Hive was performed. The results of the research could be used in the course of scientific and training experiments of organization when implementing the most modern IT-technologies.

Mudcake effects on wellbore stress and fracture initiation pressure and implications for wellbore strengthening

Although a large volume of mudcake filtration test data is available in the literature, effects of mudcake on wellbore strengthening cannot be quantified without incorporating the data into a stress-analysis model. Traditional models for determining fracture initiation pressure (FIP) either consider a wellbore with an impermeable mudcake or with no mudcake at all. An analytical model considering permeable mudcake is proposed in this paper. The model can predict pore pressure and stress profiles around the wellbore, and consequently the FIP, for different mudcake thickness, permeability, and strength. Numerical examples are provided to illustrate the effects of these mudcake parameters. The results show that a low-permeability mudcake enhances FIP, mainly through restricting fluid seepage and pore pressure increase in the near-wellbore region, rather than by mudcake strength. Fluid loss pressure (FLP) should be distinguished from FIP when a mudcake is present on the wellbore wall. Fracture may occur behind the mudcake at FIP without mudcake rupture. The small effect of mudcake strength on FIP does not mean its effect on FLP is small too. Mudcake strength may play an important role in maintaining integrity of the wellbore once a fracture has initiated behind the mudcake.

Temperature and data size trade-off in dictionary based test data compression

This paper proposes a new thermal-aware test data compression technique using dictionary-based coding. Large test data volume and rise in chip temperature during a test, are the two major challenges for the test engineers. Efficient filling of the don't care bits of the test patterns minimises the transition count in the scan chains, which in turn reduces the temperature of the chip to a large extent. On the other hand, high test data compression can be achieved by filling the don't-cares in a manner to get more similar sub-vectors within the test vectors. Although, both the problems rely on don't-care bit filling, most of the existing works have considered them separately. Moreover, it has been observed that, in general, thermal-aware don't-care filling leads to poor test compression, while a compression-aware don't-care filling produces high temperature. However, a high test compression with low-temperature is the most desirable expectation. In our work, we have combined the temperature reduction and the test data compression into a single problem and solved it. We have presented an integrated approach that can perform a trade-off between temperature and test compression. Experimental results on ISCAS'89, ITC'99 and IWLS'05 benchmarks show the flexibility of the proposed method to achieve a balance between temperature and test compression. The work has further been extended to reduce temperature without sacrificing compression.

System-on-Chip Test Data Compression Based on Split-Data Variable Length (SDV) Code

System-on-a-chips with intellectual property cores need a large volume of data for testing. The large volume of test data requires a large testing time and test data memory. Therefore new techniques are needed to optimize the test data volume, decrease the testing time, and conquer the ATE memory limitation for SOC designs. This paper presents a new compression method of testing for intellectual property core-based system-on-chip. The proposed method is based on new split- data variable length (SDV) codes that are designed using the split-options along with identification bits in a string of test data. This paper analyses the reduction of test data volume, testing time, run time, size of memory required in ATE and improvement of compression ratio. Experimental results for ISCAS 85 and ISCAS 89 Benchmark circuits show that SDV codes outperform other compression methods with the best compression ratio for test data compression. The decompression architecture for SDV codes is also presented for decoding the implementations of compressed bits. The proposed scheme shows that SDV codes are accessible to any of the variations in the input test data stream.

Reduced-code test method using sub-histograms for pipelined ADCs

The measurement of static test parameters for an analog-todigital converter (ADC) requires a large volume of test data, especially for a high-resolution ADC. This paper proposes a reduced-code test method for pipelined ADCs that does not compromise test accuracy. The proposed method calculates fault information at each stage by using sub-histograms. The simulation results based on 12-bit pipelined ADCs show a maximum integral nonlinearity error of 0.590 LSB with only 3.92% of the codes required for the conventional histogram-based method.

A Novel Architecture for Scan Cell in Low Power Test Circuitry

Over the past decade VLSI manufacturing industry flourishing very rapidly. Now a days hundreds and thousands of millions of transistors that are incorporated on a chip. As the circuit complexity increasing design for test circuitry also became more complex. These complex test circuitry heavily stressed to check the functionality of the CUT (Circuit under Test). Compared with normal functional mode, Power dissipation during test mode is much higher. Power dissipation during testing is more than twice compared with normal functional mode. Large Test data volume and High power consumption are the main problems in Design for Testability. This excessive power consumption is mainly due to switching of the scan cells. The technique proposed in this paper reduces switching activity in the scan cells there by the power consumption during testing can be reduced. In the proposed scan cell architecture some of the idle flip-flops are disabled during scanning using a control signal. By disabling idle flip-flops can be possible by an external control signal or with any internal signal. Excessive power consumption during testing may cause performance degradation and high system cost. These problems can be eliminated with the proposed scan cell architecture.

FPGA IMPLEMENTATION OF RUN LENGTH ENCODING WITH NEW FORMULATED CODEWORD GENERATOR

There are two major impacts in today industry while testing larger integrated circuits like large test data volume and high test power. In our proposed scheme target both two issues for achieving two aforementioned goals in full scan sequential circuits. Shift power is reduced by one of the adjacent filling. During testing we are filling the unspecified bits in the test pattern with either 0’s or 1’s depend on nearest specified bit from left side. After filling the don’t care bits test data can be compressed by shifted alternate frequency directed run length encoding. A new formulated codeword generator is introduced and it generates infinite number of codeword for large size input test pattern. Using this codeword generator test data volume can be effectively compressed. The experimental results on ISCAS’89 benchmark circuit shows our scheme provides better efficiency as well as significant reduction in test power.

Test Data Compression Using Variable Prefix Run Length (VPRL) Code

One of the major challenges in testing a system-on-a-chip (SoC) is dealing with the large test data volume and large scan power consumption. To reduce the volume of test data, several test data compression techniques have been proposed. This paper presents a new test data compression scheme, which reduces test data volume for a system-on-a-chip (SoC). The proposed approach is based on the use of MT (Minimum Transition)-fill technique and Variable Prefix Run Length (VPRL) codes for test data compression. These VPRL codes can efficiently compress the data streams, that are composed of both runs of 0s and 1s. Experimental results for ISCAS’89 benchmark circuits supports and proves the proposed approach, better to the other existing techniques, by reducing test data volume.

Observation-Oriented ATPG and Scan Chain Disabling for Capture Power Reduction

Eliminating the excessive test power for integrated circuits is a strict challenge within the nanometer era. This method combines test pattern generation with the scan chain disabling technique to achieve low capture power testing under the single stuck-at fault model. Testability analysis is exploited to assist in the test pattern generation process to generate the observation-oriented test patterns. In order to direct fault effects to the frequently-used circuit outputs, unbalanced observability costs are purposely assigned to circuit outputs to introduce unequal propagation probability. Observation-aware scan chain clustering is then performed through a weighted compatibility analysis to densely cluster the frequently-used scan cells into scan chains. Consequently, more scan chains can be disabled in the capture cycle and significant power reduction can be achieved without affecting the fault coverage. To simultaneously consider the reduction in large test data volume and capture power, the power-aware test vector compaction algorithm is also performed. Experimental results for the large ISCAS'89 benchmark circuits show that significant improvements can be simultaneously achieved including 71.7 % of capture power reduction, 43.7 % of total power reduction, 24.3 % of peak power reduction and 98.0 % of test data compaction ratios averagely. Results for three large ITC'99 benchmark circuits also demonstrate the effectiveness of the proposed method for the practical-scale circuits.

Adapting Scan Based Test Vector for Compression Method Based On Transition Technique

Present complexity of System on Chip (SoC) design is increasing rapidly in the number of test patterns, huge switching activity and its transition time. This large test data volume is becoming one of the major problems in association with huge switching activity and its corresponding response time. This paper considers the problem of huge test pattern in scan based design. This proposed algorithm is based on reducing test pattern on scan shift in operation. This is achieved by identifying test data transition and equally segmenting the scan based test patterns. Each scan test pattern is considered by its transition and segmented into equal necessary blocks. This finally gives the compressed test patterns in reduced test patterns. Theoretical analysis and experimental results on ISCAS89 shows that the proposed method reduces test pattern by 37% when compared to the traditional approaches.

On Reducing Test Power and Test Volume by Selective Pattern Compression Schemes

In modern chip designs, test strategies are becoming one of the most important issues due to the increase of the test cost, among them we focus on the large test power dissipation and large test data volume. In this paper, we develop a methodology to suppress the test power to avoid chip failures caused by large test power, and our methodology is also effective in reducing the test data volume and shift-in power. The proposed schemes and techniques are based on the selective test pattern compression, they can reduce considerable shift-in power by skipping the switching signal passing through long scan chains. The experimental results with ISCAS89 circuits demonstrate that our methodology can achieve significant improvement in the reduction of shift-in power and test data volume. Our approach also supports multiple scan chains.

Deterministic built-in self-test using multiple linear feedback shift registers for test power and test volume reduction

Large test data volume and excessive test power are two strict challenges for very large-scale integration testing. This study presents a deterministic built-in self-test scheme using variable-length multiple linear feedback shift registers to generate the compressed low power test set. The experimental results show that both test power and test application time can be reduced significantly.

Test Data Compression Using Multi-dimensional Pattern Run-length Codes

Test data compression is an efficient methodology in reducing large test data volume for system-on-a-chip designs. In this paper, a variable-to-variable length compression method based on encoding runs of compatible patterns is presented. Test data in the test set is divided into a number of sequences. Each sequence is constituted by a series of compatible patterns in which information such as pattern length and number of pattern runs is encoded. Theoretical analyses on the evolution of the proposed Multi-Dimensional Pattern Run-Length Compression (MD-PRC) are made respectively from one-Dimensional-PRC to three-Dimensional-PRC. To demonstrate the effectiveness of the proposed method, experiments are conducted on both larger ISCAS'89 benchmarks and the industrial circuits with large number of don't cares. Results show this method can achieve significant compression in test data volume and have good adaptation to industrial-size circuits.

Test data compression for system-on-a-chip using extended frequency-directed run-length code

One of the major challenges in testing a system-on-a-chip is dealing with the large volume of test data. To reduce the volume of test data, several test data compression techniques have been proposed. Frequency-directed run-length (FDR) code is a variable-to-variable run length code based on encoding runs of 0s. It is demonstrated that higher test data compression can be achieved based on encoding both runs of 0s and 1s. An extension to the FDR code is proposed and by experimental results its effectiveness in achieving a higher compression ratio is demonstrated.

Strength and Ductility of Confined Concrete

An analytical model is proposed to construct a stress‐strain relationship for confined concrete. The model consists of a parabolic ascending branch, followed by a linear descending segment. It is based on calculation of lateral confinement pressure generated by circular and rectilinear reinforcement, and the resulting improvements in strength and ductility of confined concrete. A large volume of test data, including poorly confined and well‐confined concrete was evaluated to establish the parameters of the analytical model. Confined concrete strength and corresponding strain are expressed in terms of equivalent uniform confinement pressure provided by the reinforcement cage. The equivalent uniform pressure is obtained from average lateral pressure computed from sectional and material properties. Confinement by a combination of different types of lateral reinforcement is evaluated through superposition of individual confinement effects. The descending branch is constructed by defining the strain corresponding to 85% of the peak stress. This strain level is expressed in terms of confinement parameters. A constant residual strength is assumed beyond the descending branch, at 20% strength level. The model is compared against a large number of column tests. Circular, square, and rectangular columns, with spiral and rectilinear reinforcements, as well as welded wire fabric, are used for comparison. Comparisons include concentric and eccentric loadings, as well as slow and fast strain rates. The results indicate good agreement.