FPGA IMPLEMENTATION OF RUN LENGTH ENCODING WITH NEW FORMULATED CODEWORD GENERATOR

Abstract

There are two major impacts in today industry while testing larger integrated circuits like large test data volume and high test power. In our proposed scheme target both two issues for achieving two aforementioned goals in full scan sequential circuits. Shift power is reduced by one of the adjacent filling. During testing we are filling the unspecified bits in the test pattern with either 0’s or 1’s depend on nearest specified bit from left side. After filling the don’t care bits test data can be compressed by shifted alternate frequency directed run length encoding. A new formulated codeword generator is introduced and it generates infinite number of codeword for large size input test pattern. Using this codeword generator test data volume can be effectively compressed. The experimental results on ISCAS’89 benchmark circuit shows our scheme provides better efficiency as well as significant reduction in test power.