Abstract
One of the major challenges in testing a system-on-a-chip (SoC) is dealing with the large test data volume and large scan power consumption. To reduce the volume of test data, several test data compression techniques have been proposed. This paper presents a new test data compression scheme, which reduces test data volume for a system-on-a-chip (SoC). The proposed approach is based on the use of MT (Minimum Transition)-fill technique and Variable Prefix Run Length (VPRL) codes for test data compression. These VPRL codes can efficiently compress the data streams, that are composed of both runs of 0s and 1s. Experimental results for ISCAS’89 benchmark circuits supports and proves the proposed approach, better to the other existing techniques, by reducing test data volume.
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