A variable-length compatible compression scheme based on tristate signals

Abstract

The test data volume for the manufacturing test of chips is increasing rapidly. This is due to the fact that the complexity of these chips is increasing rapidly and the transistor count is increasing exponentially. Aimed at solving the problems of large test data volume and long test time in chips test, this paper presents a deterministic test-based compression method that uses tristate signals encoding and compatible test cube merging. Firstly, the partial input reduction is carried out for the original test set. The proportion of “don’t care” bits in the original test set is increased by merging compatible or inversely compatible inputs in the test cubes, so the compatibility among the test cubes is improved. Then, the test set is compressed and encoded by using tristate signal. Each test cube is divided into several data segments, which are encoded by tristate signals and multiple compatibility rules. This scheme can improve the compression ratio of the test set. The experimental results show that the proposed scheme achieves a good compression ratio, without excessive test power and area overhead. The average test compression ratio can reach 82.15%.