System-on-Chip Test Data Compression Based on Split-Data Variable Length (SDV) Code

J Robert Theivadas,J Raja Paul Perinbam,V Ranganathan

doi:10.4236/cs.2016.78105

Abstract

System-on-a-chips with intellectual property cores need a large volume of data for testing. The large volume of test data requires a large testing time and test data memory. Therefore new techniques are needed to optimize the test data volume, decrease the testing time, and conquer the ATE memory limitation for SOC designs. This paper presents a new compression method of testing for intellectual property core-based system-on-chip. The proposed method is based on new split- data variable length (SDV) codes that are designed using the split-options along with identification bits in a string of test data. This paper analyses the reduction of test data volume, testing time, run time, size of memory required in ATE and improvement of compression ratio. Experimental results for ISCAS 85 and ISCAS 89 Benchmark circuits show that SDV codes outperform other compression methods with the best compression ratio for test data compression. The decompression architecture for SDV codes is also presented for decoding the implementations of compressed bits. The proposed scheme shows that SDV codes are accessible to any of the variations in the input test data stream.

Highlights

One of the important objectives of detailed testing of VLSI circuits and systems isHow to cite this paper: Theivadas, J.R., Ranganathan, V. and Perinbam, J.R.P. (2016) System-on-Chip Test Data Compression Based on Split-Data Variable Length (SDV) Code
VLSI technology has made the testing of ICs complex and time consuming resulting in the increased cost of the ICs
For B = 2, 2 LSB splits-off and so Run Length Coding (RLC) is performed as 3 zeroes + 1 resulting in 6 bits (2LSB + RLC- > 11 + 3 zeroes + 1)

Summary

Introduction

One of the important objectives of detailed testing of VLSI (very large scale integration) circuits and systems isHow to cite this paper: Theivadas, J.R., Ranganathan, V. and Perinbam, J.R.P. (2016) System-on-Chip Test Data Compression Based on Split-Data Variable Length (SDV) Code. Each of these steps has its own flaws These flaws may lead to failure in the operation of the individual ICs. VLSI technology has made the testing of ICs complex and time consuming resulting in the increased cost of the ICs. The problems related to testing have enormously intensified in case of SOC (System on Chip) because of the large numbers of IP (Intellectual Property) cores on a single silicon chip. The problems related to testing have enormously intensified in case of SOC (System on Chip) because of the large numbers of IP (Intellectual Property) cores on a single silicon chip This huge reduction in the circuit size has increased the sensitivity to performance variations and they still require complete testing before they are shipped to the customers. It can be taken as an approach to validate the design and check the process involved

Methods

Results

Conclusion