Capture in Turn Scan for Reduction of Test Data Volume, Test Application Time and Test Power

Abstract

With the exponential increase of transistor counts, scan design encounters several problems such as large test data volume, long test application time and high test power. In this paper, we propose a new method to reduce test data volume, test application time and also average and peak power during test. The proposed method is based on a scan chain disabling technique where only one internal sub scan chain is active at a time. Though our method makes a sacrifice of test generation time, instead, we can achieve reduction of test data volume, test application time and test power together. Experimental results show the effectiveness of the proposed method.