Fast circuit topology based method to configure the scan chains in Illinois Scan architecture

Abstract

High test data volume and long test application time are two major concerns for testing scan based circuits. The Illinois Scan (ILS) architecture has been shown to be effective in addressing both these issues. The ILS achieves a high degree of data compression thereby reducing both test data volume and test application time. However, the fault coverage achieved in the Broadcast Mode of the ILS architecture depends on the actual configuration of individual scan chains, i.e., the number of chains and the mapping of the individual flip-flops of the circuit to the respective scan chain positions. Current methods for constructing scan chains in the ILS are either ad-hoc or rely on test pattern information from an apriori ATPG run. In this paper, we present a novel low cost technique to construct ILS scan configuration for a given design. It efficiently utilizes the circuit topology and tries to optimize the flip-flop assignment to a scan chain location without compromising the fault coverage in the Broadcast Mode. Thus, it eliminates the need of an apriori ATPG run or any test set information. Experimental results on the ISCAS'89 benchmark circuits show that the proposed ILS configuration method can achieve on an average 5% more fault coverage in the Broadcast Mode and an average 15% more reduction in total test data volume and test application time than the existing methods.