Large Threshold Voltage Shift Research Articles

MoS2-Based MOS Capacitor for In-Memory Light Sensing

Recently, two-dimensional transition metal dichalcogenide (2D-TMD) materials have shown great attention due to their special physical characteristics and their applications in nanodevices [1]. The 2D-TMD materials are possible to develop via chemical vapor deposition (CVD) and physical and chemical exfoliation methods. The mechanical exfoliation method is very promising to the growth of high quality TMDs like MoS2, WS2, ZrS2, MoSe2, NbSe2, and WSe2 [2]. Along with other 2D materials, MoS2 has been used as a channel material in field effect transistors due to its transition from indirect bandgap to direct bandgap. This bandgap is sufficient to balance the limitations of the zero-bandgap graphene for electronic devices [3]. Moreover, researchers have reported that the threshold voltage of the memory or transistor could be shifted when optical light is illuminated. The memory window of the transistor is modulated using the different wavelengths of light. The phenomenon is primarily based on the application of photo-induced charge carriers. The light induced threshold voltage shifting with bias voltage confirms the possibility to use photo-generated carriers in in-memory light sensors [4].MOS capacitor was fabricated on Si substrate. A 3 nm thick Al2O3 tunneling layer was deposited by plasma enhanced atomic layer deposition (PE-ALD) at 2500 C. Next, a 70-nm thick MoS2 was deposited using the drop casting. A 7 nm thick Al2O3 was again deposited by PE-ALD as a blocking layer at 2500 C. Finally, 50 nm thick Al film was deposited as a top electrode by sputter using a metal shadow mask. The complete fabrication process of the Al/Al2O3/MoS2/Al2O3/P+-Si MOS devices is shown in Fig. 1.The charging properties of the device were measured, as shown in Fig. 2. The device was operated with sweep voltage of +6/-6 V in forward and reverse conditions, as depicted in Fig. 2 (a). The memory window of the device was examined of about 2.5 V. To confirm the long-term stability, the endurance of the device was measured with the programming and erasing voltages of +6/-6 and -6/+6, respectively (Fig 2 (b)). The device demonstrates good endurance for more than 1000 cycles. We also measured the memory window of the device by increasing the sweeping voltages from +4/-4 to +8/-8 during the programming and erasing conditions, which is depicted in Fig. 2(c). The memory window was increased with increasing the sweeping voltages and the noted maximum was about 5 V at +8/-8 V, suggesting superb charge trapping effect. The optical characteristics of the device were examined by illuminating light onto the device. The optical features of the device were determined using the different wavelength of light from 600 nm to 450 nm. When the device was in dark, the memory window was observed to be about 2.5 V. When the optical light (Intensity: 2 mW/cm2) was turned on for 1 s onto the device with 600 nm wavelength during the programming of +6/-6 V, the threshold voltage was increased from 2.5 V to 3.2 V. We further checked the effect of different wavelengths of light from 550 nm to 450 nm with the interval of 50 nm using the same programming voltage, same intensity, and same illumination time. We got an enormous shift in threshold voltage from 3.2 V to about 5 V. The large threshold voltage shift confirms the MoS2 layer traps more electrons for 450 nm wavelength.The MOS device displays a decent memory window (2.5 V) and good endurance (1000cycles) without any humiliation. The MOS device reveals a great memory window when the operating voltage was varied from 4/-4 to 8/-8. The memory window of the MOS device was increased from 2.5 V to about 5 V when optical light with different wavelengths was induced onto the device. These decent features of the device make it highly applicable for storage and in memory light sensing in the near future.References Konstantatos et al, “Hybrid graphene–quantum dot phototransistors with ultrahigh gain. Nature Nanotech”, vol 7, pp. 363–368, 2012Shanmugam et al, “A Review of the Synthesis, Properties, and Applications of 2D Materials. Particle, vol 39, 2200031, 2022F. Mak et al, “Atomically Thin MoS2: A New Direct-Gap Semiconductor”, Phys. Rev. Lett, vol 105, 136805, 2010.Hu et al, “Dependency of organic phototransistor properties on the dielectric layers”, Appl. Phys. Lett. vol 89, 072108, 2006 Fig. 1. Schematic of complete fabrication process of the MOS deviceFig. 2. (a) C-V curve of the device. (b) Endurance of the device. (c) C-V curve with the sweeping voltages of +4/-4 to +8/-8 in the programming and erasing. Figure 1

Observation of Large Threshold Voltage Shift Induced by Pre-applied Voltage to SiO2 Gate Dielectric in Organic Field-Effect Transistors

Field-effect transistors based on organic semiconducting materials (OFETs) have unique advantages of intrinsically mechanical flexibility, simple preparation process, low manufacturing cost, and large-area preparation. Through the innovation of new material design and device structures, the performance of device parameters such as mobility, on–off current ratio, and the threshold voltage (VTH) of OFETs continues to improve. However, the VTH shift of OFETs has always been an important problem restricting their practical applications. In this work, we observe that the VTH of polymer OFETs with the widely investigated device structure of a SiO2 bottom-gate dielectric is noticeably shifted by pre-applying a large gate voltage. Such a shift in VTH remains to a large extent, even after modifying the surface of the SiO2 dielectric using a hexamethyldisilazane (HMDS) self-assembled monolayer. This behavior of VTH can be ascribed to the charge trappings at the bulk of the SiO2. In addition, the generality of this observation is further proven by using two other conjugated polymers including p-type PDPP3T and n-type PTzNDI-2FT, and a similar trend is obtained.

Organic Phase-Change Memory Transistor Based on an Organic Semiconductor with Reversible Molecular Conformation Transition.

Phase-change semiconductor is one of the best candidates for designing nonvolatile memory, but it has never been realized in organic semiconductors until now. Here, a phase-changeable and high-mobility organic semiconductor (3,6-DATT) is first synthesized. Benefiting from the introduction of electrostatic hydrogen bond (S···H), the molecular conformation of 3,6-DATT crystals can be reversibly modulated by the electric field and ultraviolet irradiation. Through experimental and theoretical verification, the tiny difference in molecular conformation leads to crystalline polymorphisms and dramatically distinct charge transport properties, based on which a high-performance organic phase-change memory transistor (OPCMT) is constructed. The OPCMT exhibits a quick programming/erasing rate (about 3 s), long retention time (more than 2h), and large memory window (i.e., large threshold voltage shift over 30V). This work presents a new molecule design concept for organic semiconductors with reversible molecular conformation transition and opens a novel avenue for memory devices and other functional applications.

Cryogenic-temperature investigation of negative bias stress inducing threshold voltage instabilities on 4H-SiC MOSFETs

We investigate the effect of Negative-Bias-Temperature-Instability on 4H-Silicon Carbide MOSFETs at room and cryogenic temperature and found a large negative threshold voltage shift at T < 250 K. For T < 140 K, both capture and emission follow an almost ideal exponential transient. Cryogenic temperatures reveal fast interface traps, otherwise difficult to probe at relatively high temperatures; we attribute the threshold voltage shift to a high density of hole traps located: 1) close to the SiC valence band and able to emit within the measurement time window; 2) above the SiC valence band, responsible of the slow transient at low temperature. Finally, the extraction of the emission time constant via Capture Emission Time map analysis allowed to extract the activation energy of mechanism 2 (82 meV).

Electrical defect passivation of nanocrystalline In-Ga-O thin film transistor with organic-inorganic superlattice structure

ABSTRACT Metal oxide thin film transistors have received tremendous attention due to various advantages over the conventional Si-based TFT for the next-generation wearable electronics. However, the surface of a metal oxide thin film is very sensitive to ambient molecules such as moisture and oxygen, degrading the device performance after long-term operation. In this work, we report on utilizing the passivation effect from various phosphonic acids (PAs) to suppress the adsorption of ambient chemical species and the oxygen vacancy defect in the superlattice (SL) structure prepared by insertion of PA between two nanocrystalline In-Ga-O (nc-IGO) layers (7.5% atomic percentage). The most effective stabilization of SL structure is successfully realized with 1,10-decyl diphosphonic acid (P10) treatment. Very impressively, the reference device with pristine nc-IGO film around 10 nm shows a large threshold voltage (Vth) shift of 11.80 V after 10,000 s of PBS (VG = 50 V, VDS = 25 V), but the optimized device with P10 SL structure with similar thickness shows a negligible Vth of 1.21 V with same stress condition. Furthermore, the oxygen vacancy defect suppression also resulted in a small Vth shift of 2.94 V after 10,000 s NBS (VG = −50 V, VDS = −25 V).

Perhydropolysilazane Charge‐Trap Layer in Solution‐Processed Organic and Oxide Memory Thin‐Film Transistors

AbstractThe charge trapping property of spin‐coated perhydropolysilazane (PHPS) layers for solution‐processed organic and oxide thin film memory transistors is demonstrated. The nitrogen content within the PHPS layer is decreased by increasing the annealing temperatures from room temperature to 450 °C. The PHPS layer added to the SiO2 gate insulator in the charge trap memories (CTMs) shows good memory functionalities which are electrically programmable, and is erased either electrically or optically depending on the semiconductor used. The stored or erased charges in the p‐type semiconductor‐based CTM result in relatively large threshold voltage shifts (∆VTH &gt; 60 V) and large memory on‐ and off‐current ratio (IM,ON/IM,OFF &gt; 103) with the respective memory output current extrapolated to 108 s. The n‐type CTM shows ∆VTH ≈ 20 V, IM,ON/IM,OFF of 0.5 × 103 and is extrapolated to 1015 s. It is concluded that the origin of the charge‐traps in both the p‐type and n‐type CTMs mainly originates from the PHPS charge trap layer (CTL) and greatly occurs in highly concentrated nitrogen PHPS layers. There is a high possibility of using the PHPS CTL in a wide variety of cost‐effective CTMs even with high temperature processed semiconductors.

Understanding High-Energy 75-MeV Sulfur-Ion Irradiation-Induced Degradation in GaN-Based Heterostructures: The Role of the GaN Channel Layer

AlInN/GaN on Si high-electron mobility transistors (HEMTs) are irradiated with various fluences of 75-MeV sulfur ions to study the radiation-induced degradation mechanisms. Heavy-ion irradiation has been found to reduce saturation ON- and OFF-state current and, at higher fluence, to induce a large positive threshold voltage shift. Irradiated structures reveal a consistent carrier density and mobility reduction as a function of fluence. To demonstrate the buffer-induced threshold shift, a series of samples with various GaN channel layer thicknesses defined by carbon-doped GaN buffer layers are characterized. By comparison of the threshold voltage of nonirradiated devices with reduced channel layer thickness, we assign the observed effects mainly to carrier depletion. Thus, formation of acceptor-like traps upon irradiation is concluded as primary degradation mechanism in GaN-based HEMTs. AlInN/GaN HEMT structures are, therefore, more tolerant to heavy-ion irradiation than AlGaN/GaN transistors as their intrinsic channel conductivity is higher.

High-Accuracy Deep Neural Networks Using a Contralateral-Gated Analog Synapse Composed of Ultrathin MoS₂ nFET and Nonvolatile Charge-Trap Memory

The development of high-accuracy analog synapse deep neural networks entails devising novel materials and innovative memory structures. We demonstrated an analog synapse with contralateral gates based on a two-dimensional (2D) field-effect transistor and nonvolatile charge-trap memory. Vertical integration of a MoS2-channel FET with a charge-trapping layer provided excellent charge controllability and gate-tunable nonvolatile storage. In the proposed contralateral-gate design, the read and write operations were separated to mitigate read disturb degradation. Reducing the MoS2channel thickness to the ultrathin scale allowed large threshold voltage shifts and on-resistance ( $\text{R}_{\text {ON}}$ ) modulations. This vertically integrated MoS2synapse device exhibited 55 conductance states, high conductance max–min ratio ( ${G}_{\text {MAX}}/ ~{G}_{\text {MIN}}$ ; ~50), low nonlinearity of $\alpha _{\text {p}}$ = −0.81 and $\alpha _{\text {d}}$ = −0.31, near ideal asymmetry of 0.5, and free of read disturb degradation. High neural network accuracy (>87%) is also obtained.

Effect of overdrive voltage on PBTI trapping behavior in GaN MIS-HEMT with LPCVD SiNx gate dielectric**Project supported by the National Key Research and Development Program, China (Grant No. 2017YFB0402800), the Key Research and Development Program of Guangdong Province, China (Grant No. 2019B010128002), the National Natural Science Foundation of China (Grant No. U1601210), and the Natural Science Foundation of Guangdong Province,

The effect of high overdrive voltage on the positive bias temperature instability (PBTI) trapping behavior is investigated for GaN metal–insulator–semiconductor high electron mobility transistor (MIS-HEMT) with LPCVD-SiNx gate dielectric. A higher overdrive voltage is more effective to accelerate the electrons trapping process, resulting in a unique trapping behavior, i.e., a larger threshold voltage shift with a weaker time dependence and a weaker temperature dependence. Combining the degradation of electrical parameters with the frequency–conductance measurements, the unique trapping behavior is ascribed to the defect energy profile inside the gate dielectric changing with stress time, new interface/border traps with a broad distribution above the channel Fermi level are introduced by high overdrive voltage.

Comparison of Extremely High-Temperature Characteristics of Planar and Three- Dimensional SiC MOSFETs

We demonstrated differences in the characteristics of planar and three-dimensional SiC MOSFETs at extremely high temperatures (around 500°C). There is a large threshold-voltage shift (ΔV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> ) from 25 to 500°C in the SiC MOSFETs. The V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> of the three-dimensional SiC MOSFET is half that of the planar SiC MOSFET. A large amount of electron emissions from shallow interface traps causes the ΔV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> and is likely to affect the robustness of SiC MOSFETs against short circuits.

Bias Temperature Stress Instability of Multilayered MoS2 Field-Effect Transistors With CYTOP Passivation

Bias temperature stress instability on multilayered MoS2 FETs was systematically investigated with the device scheme encapsulated with amorphous fluoropolymers [cyclized transparent optical polymer (CYTOP)] for the secure of minimization of external gas ambient effects. Large threshold voltage shifts ( $\Delta {V}_{\textsf {th}}$ ) for the negative bias temperature stress (NBTS) were observed, compared to the positive bias temperature stress (PBTS). Herein, the asymmetry behaviors on $\Delta {V}_{\textsf {th}}$ , observed in this paper, are ascribed to the sulfur vacancy in MoS2 layers, leading to large hole traps compared to electron traps in MoS2 layers. Moreover, high-temperature-sensitivity [ ${d}$ ( $\Delta {V}_{\textsf {th}}$ )/ dT ] on $\Delta {V}_{\textsf {th}}$ for PBTS than NBTS was observed, and their origins are possibly due to synergetic effects associated with large trap energy distribution ( ${k}_{o}{T}$ ) for electron trap levels.

Distinct characteristics of DNA field effect transistors embedded with marine-derived porphyra-334 under UV illumination

DNA extracted from salmon has recently attracted the attention of researchers, resulting in applications of DNA in photonic and electronic devices. Porphyra-334, a type of mycosporine-like amino acids (MAAs), also plays an important role in photoprotection for a variety of marine organisms including bacteria and algae. Although MAA and DNA molecules have been intensively studied, fabrication methodology and applicability of MAA-embedded DNA complexes for physical applications have been seldom discussed due to incompatibility between biological samples and physical platform. Here, Porphyra-334 embedded DNA was investigated to understand its electrical transport property with the aid of silicon nanowire/nanoribbon field effect transistors (NW/NR FETs). Its chemical stability was determined by cyclic voltammetry upon illumination of UV light. The current of DNA-SiNW FET was enhanced by the addition of Porphyra-334 and upon illumination of UV light. Conductivities of PDNA-SiNW FET compared to SiNW FET were increased up to ∼70% at dark and ∼40% under UV light due to the presence of Porphyra-334 and excess injection of charge carriers in Porphyra-334 embedded DNA generated by absorbing UV light, respectively. The addition of Porphyra-334 in DNA-SiNR FET lowered its energy level and resulted in large threshold voltage shift towards the negative scale. In addition, its electrochemical property was studied by cyclic voltammetry and impedance spectroscopy. Porphyra-334 in DNA solution which inhibited oxidation of DNA showed relatively lower current indicating high electrochemical stability and decrease of resistance compared to pristine DNA solution based on results of impedance spectroscopy.

Effects of trifluoromethyl substituents on interfacial and bulk polarization of polystyrene gate dielectrics

The ability to control the bulk and interfacial polarization of dielectric polymers is important to their application in organic electronics. We examine the effect of the trifluoromethyl substituent on poly(3-trifluoromethylstyrene) (P3TFMS) as compared to unsubstituted polystyrene (PS) on the I-V relationships of pentacene-based organic field-effect transistors (OFETs). Single- and double-layered films of these polymers were used, with lower layers crosslinked through vinylbenzocyclobutene comonomers before deposition of upper layers. Control experiments verified that the electronic effect of the crosslinking was negligible. We found that the TFM substituent markedly and independently affected both the initial threshold voltage Vth and the nonvolatile, shifted Vth observed after the application of static gate voltage, depending on its position adjacent or apart from the pentacene. The trifluoromethyl-bearing polymers exhibited significantly lower magnitude initial threshold voltages (Vth,i of ca. −17 V for P3TFMS compared to −35 V for PS), large threshold voltage shifts after charging by the application of static electric fields (ΔVth of ca. 32 V for P3TFMS and 17 V for PS), and greater stability of the ΔVth under repeated charge/discharge cycles. These results are consistent with P3TFMS having fewer interfacial trap states but more stable bulk trap states. The results are applicable to organo-electronic systems such as piezoelectrics for energy harvesting and nonvolatile OFETs such as memory, sensing, and logic elements.

Optical memory characteristics of solution-processed organic transistors with self-organized organic floating gates for printable multi-level storage devices

Abstract Exploring optical memory functions in nonvolatile organic field-effect transistor (OFET) memories with top-gate/bottom-contact (TG/BC) configurations can offer effective routes for developing printable, high-density organic memory circuits capable of multi-level data storage. Here, we use a solution process to fabricate TG/BC OFET devices with organic floating-gate structures and investigate their memory characteristics under light illumination. A solution-processable organic composite of 6,13-bis(triisopropylsilylethynyl)pentacene (TIPS-pentacene) and poly(methylmethacrylate) is employed to self-organize organic floating-gate structures on a solution-processed semiconductor layer composed of poly(3-hexylthiophene) (P3HT). The floating-gate OFET devices programmed with blue, green, and red light exhibit large threshold voltage (Vth) shifts of approximately 30 V and stable charge retention characteristics even under light illumination. The devices also exhibit high sensitivity to incident light during programming, and the degree of Vth shift and the on-state current can be tuned using light and programming voltage to facilitate distinct storage and readout of multi-level data.

0.9-A/mm, 2.6-V Flash-Like Normally-Off Al2O3/AlGaN/GaN MIS-HEMTs Using Charge Trapping Technique

Flash-like Al2O3/AlGaN/GaN metal–insulator–semiconductor high electron mobility transistors (MIS-HEMTs) were fabricated using a charge trapping technique. These MISHEMTs showed a large threshold voltage ( ${V}_{\text {th}}$ ) shift of 9.35 V after applying a 10-V program voltage ( ${V}_{P}$ ), resulting in a normally-off device with a high ${V}_{\text {th}}$ of 2.6 V and a high maximum drain current ( ${I}_{\mathrm {dmax}}$ ) of 0.9 A/mm. The ${V}_{\text {th}}$ dependence on ${V}_{P}$ was analyzed and $V_{\text {th}}$ was above 0 V for ${V}_{P} = 8$ V. Photo-assisted $C$ – $V$ measurements revealed that the traps contributing to the large ${V}_{\text {th}}$ shift had a density of $2.18\times 10^{13}$ cm−2 and the activation energy for the photo-assisted de-trapping process ranged from 2.67 to 3.06 eV. These traps were attributed to border or oxide defects. The retention level of the device was up to 102 s after applying 10-V ${V}_{P}$ . These results indicate that the charge trapping method with a single Al2O3 dielectric is a promising way to achieve normally-off devices with both high ${V}_{\mathrm {th}}$ and high ${I}_{\mathrm {dmax}}$ .

Near infrared-induced optical gating at the lead-sulfide (PbS)/pentacene interface

We report optical gating at the pentacene/lead sulfide (PbS) functional interface through which mobile carriers are confined in the pentacene layer close to the PbS colloidal quantum dot (CQD) layer. Using a bottom-contact pentacene/PbS field effect transistor (FET) structure, hole doping in a pentacene layer is demonstrated and the mechanism by which mobile carriers are created is elucidated by probing threshold voltage shift in the FET and the pentacene/PbS interfacial trap density. A large threshold voltage shift under selective illumination (780 nm) of the PbS CQD layer is interpreted as signature of hole transfer from the PbS to the pentacene. Electron trapping at the pentacene/PbS interface is suggested to be involved in the optical gating process.

Graphene quantum dot (GQD)-induced photovoltaic and photoelectric memory elements in a pentacene/GQD field effect transistor as a probe of functional interface

Electric field-induced charge trapping and exciton dissociation were demonstrated at a penatcene/grapheme quantum dot (GQD) interface using a bottom contact bi-layer field effect transistor (FET) as an electrical nano-probe. Large threshold voltage shift in a pentacene/GQD FET in the dark arises from field-induced carrier trapping in the GQD layer or GQD-induced trap states at the pentacene/GQD interface. As the gate electric field increases, hysteresis characterized by the threshold voltage shift depending on the direction of the gate voltage scan becomes stronger due to carrier trapping associated with the presence of a GQD layer. Upon illumination, exciton dissociation and gate electric field-induced charge trapping simultaneously contribute to increase the threshold voltage window, which can potentially be exploited for photoelectric memory and/or photovoltaic devices through interface engineering.

(Invited) Impact of Gate Dielectrics on the Threshold Voltage in MoS2 Transistors

The electrical characteristics of field-effect transistors based on 2D materials such as MoS2 strongly depend on defects in various regions of the device. Thus, an accurate description of charge transfer reactions with defects is essential as they have a strong impact on several important performance parameters. In particular, they disturb the electrostatic control of the gate over the channel, which is one of the central advantages of 2D devices in the ultimate scaling limit. As a consequence of charge trapping in these defects, large threshold voltage shifts are possible on short (hysteresis) and long (drift) timescales, which prohibit stable device operation. Here we introduce a driftdiffusion based simulation methodology coupled to a non-radiative multiphonon model to describe charge transfer reactions. Our results shed light on the interaction of defects with the 2D channel, which is important to enable further progress in the area of 2D based transistors.

Robust low power DC-type shift register circuit capable of compensating threshold voltage shift of oxide TFTs

This paper proposes an oxide TFT DC-type shift register that consists of eleven TFTs and one bootstrapping capacitor. The proposed circuit connects drain nodes of large size pull-up TFTs of output drivers to positive supply voltage instead of alternating clock signals for low power consumption. In addition, a robust internal inverter capable of maintaining the high voltage level of the output over the large positive threshold voltage shift by bootstrapping is implemented. For a 120Hz Full-HD display, the SPICE simulation estimates the clock power consumption of the proposed DC-type circuit as 0.56mW at 32 shift registers and ensures the robust operation over the wide range of threshold voltage shift from −4V to 10V.

Interfacial trap-induced confinement of mobile carriers during illumination at a pentacene/lead-sulfide functional interface

Interfacial electronic properties at the pentacene/lead sulfide (PbS) interface in the dark under illumination were studied. With a small size of PbS colloidal quantum dot (CQD) (2.7 nm), photoinduced charge transfer at the pentacene/PbS CQD interface leads to a large threshold voltage shift in a pentacene/PbS CQD field effect transistor (FET). Through estimation of interfacial trap density by sub-threshold slope measurements in an FET structure, the mechanism by which threshold voltage shift occurs is discussed.