Perhydropolysilazane Charge‐Trap Layer in Solution‐Processed Organic and Oxide Memory Thin‐Film Transistors

Abstract

AbstractThe charge trapping property of spin‐coated perhydropolysilazane (PHPS) layers for solution‐processed organic and oxide thin film memory transistors is demonstrated. The nitrogen content within the PHPS layer is decreased by increasing the annealing temperatures from room temperature to 450 °C. The PHPS layer added to the SiO2 gate insulator in the charge trap memories (CTMs) shows good memory functionalities which are electrically programmable, and is erased either electrically or optically depending on the semiconductor used. The stored or erased charges in the p‐type semiconductor‐based CTM result in relatively large threshold voltage shifts (∆VTH > 60 V) and large memory on‐ and off‐current ratio (IM,ON/IM,OFF > 103) with the respective memory output current extrapolated to 108 s. The n‐type CTM shows ∆VTH ≈ 20 V, IM,ON/IM,OFF of 0.5 × 103 and is extrapolated to 1015 s. It is concluded that the origin of the charge‐traps in both the p‐type and n‐type CTMs mainly originates from the PHPS charge trap layer (CTL) and greatly occurs in highly concentrated nitrogen PHPS layers. There is a high possibility of using the PHPS CTL in a wide variety of cost‐effective CTMs even with high temperature processed semiconductors.