Double Gate Junctionless Research Articles

Simulation of Junctionless Transistor for Low Power Mix Circuit

Abstract: In this work simulation of Double Gate Junction less transistor has been carried out. Comparitive study of the various parameters namely; transconductance(gm), output conductance(gd), DIBL, Subthreshold slope, Ion/Ioff, electric field and Potential. Simulation is carried out in Cogenda Visual TCAD simulator. Comparative study shows using double gate junctionless transistor reduces short channel effect such as DIBL, Subthreshold Slope, Ion/Ioff. Double Gate Junctionless transistor has higher transconductance(gm) and lower output transconductance(gd) compared to conventional junction transistor.

Design and Analysis of Recessed Double Gate Junctionless Field-Effect-Transistor Based Digital Standard Cells

Design and Analysis of Recessed Double Gate Junctionless Field-Effect-Transistor Based Digital Standard Cells

Analytical Model of Dopingless Asymmetrical Junctionless Double Gate MOSFET

Analytical Model of Dopingless Asymmetrical Junctionless Double Gate MOSFET

Study of digital/analog performance parameters of misaligned gate recessed double gate junctionless field-effect-transistor for circuit level application

In this work, the effect of gate misalignment towards the source and drain ends for 20 nm recessed double gate junctionless field-effect-transistor (R_DGJLFET) have been studied on various digital and analog performance parameters from device to circuit level while setting the simulation set-up using 2D Silvaco ATLAS technology computer aided design (TCAD). With recessed silicon channel, the quantum confinement effects have been considered for channel thickness <7 nm. In comparison to conventional double gate junctionless FET (C_DGJLFET), the device exhibits lesser OFF-current, improved ON-to-OFF current ratio, better subthreshold slope (SS), and lower drain-induced-barrier-lowering (DIBL). Analogically, it has been found that the misaligned gate towards drain affects the digital and analog parameters more severely in comparison to gate misalignment towards the source end. However, the misaligned R_DGJLFET towards the drain end shows robustness in terms of SS and DIBL with smaller variations of ∼10.84% and ∼61.79%, respectively. Moreover, due to very low parasitic capacitances, the device shows lesser variations in different alternating current (AC) performance parameters namely, transconductance generation factor (TGF), unity gain frequency, and gain-bandwidth product in comparison to C_DGJLFET. With gate misalignment towards source the unity gain frequency, and gain-bandwidth improve by ∼9.67% and ∼19.9%, respectively whereas the TGF remains almost unaffected. Furthermore, to ensure the device capability in circuit application a complementary metal-oxide-semiconductor (CMOS) inverter and common-source (CS) amplifier based on R_DGJLFET have been designed. In contrast to C_DGJLFET based counterpart, the R_DGJLFET expresses its suitability for low-power digital applications with better noise margins and smaller short-circuit current in the CMOS inverter. In analog domain, the R_DGJLFET based CS amplifier shows an improved amplification factor of 4.75 in comparison to C_DGJLFET. This paper provides deep insight into the severity of gate misalignment towards source/drain for R_DGJLFET in both digital and analog domains from device to circuit level.

Power and delay analysis of dielectric modulated dual cavity Junctionless double gate field effect transistor based label-free biosensor

Recently, Metal Oxide Semiconductor Field Effect Transistor (MOSFET) based biosensors have gained immense attraction as a diagnostic tool for point-of-care testing. This paper investigates the current sensitivity, power consumption, and intrinsic delay of the Dual Cavity Junction-less (JL) Double gate MOSFET-based biosensor. Dielectric modulation has been incorporated for label-free biosensing. The impact of neutral and charged biomolecules has been investigated on the current sensitivity, power consumption, and delay. Extensive simulation using SILVACO ATLAS has been done to study the effects. Efficacy of the dual cavity in comparison to the single cavity in JL-MOSFET is demonstrated in terms of better current sensitivity and less power consumption. This work demonstrates the low-power JL-MOSFET-based label-free biosensors for the implementation of cost-efficient and simpler analytical tools for the screening of drugs and biomolecules.

Dual P+-Wire Double-Gate Junctionless MOSFET with 10-nm Regime for Low Power Applications

Dual P+-Wire Double-Gate Junctionless MOSFET with 10-nm Regime for Low Power Applications

Nonhysteretic Condition in Negative Capacitance Junctionless FETs

This paper analyzes the design space stability of negative capacitance double gate junctionless FETs (NCDG JLFET). Using analytical expressions derived from a charge-based model, we predict instability condition, hysteresis voltage, and critical thickness of the ferroelectric layers giving rise to the negative capacitance behavior. The impact of the technological parameters is investigated in order to ensure hysteresis-free operation. Finally, the stability of NCDG JLFET is predicted over a wide range of temperatures from 77K to 400K. This approach has been assessed with numerical TCAD simulations.

Analysis of Subthreshold Swing of Symmetric Junctionless Double Gate MOSFET Using Gaussian Doping Profile

—The variation of subthreshold swing(SS) according to the projected range (Rp ) and standard projected deviation (σp ) was analyzed when the symmetrical junctionless double gate (JLDG) MOSFET was doped with Gaussian doping profile. For this purpose, the analytical SS model was presented. We compared with the TCAD results to turn out the validity of this model, and the SSs of this model agreed with those of TCAD. The effective conduction path and mean doping concentration affecting the SS were analyzed according to the Rp and σp . As a result, the SS increased as the Rp and σp increased simultaneously. The smaller the Rp and the larger the σp , the lower the SS. When Rp = 1.5 nm, it showed the SS below 100mV/dec without being affected by the change of σp or silicon thickness. When σp = 3nm, it was also 100mV/dec or less regardless of the change of Rp and silicon thickness. Keywords— Double gate, Junctionless, Subthreshold swing, Gaussian, Projected range, Standard projected deviation

High-k Dielectric Double Gate Junctionless (DG-JL) MOSFET for Ultra Low Power Applications- Analytical Model

This paper describes the impression of low-k/high-k dielectric on the performance of Double Gate Junction less (DG-JL) MOSFET. An analytical model of the threshold voltage of DG-JLFET has been presented. Poisson’s equation is solved using the parabolic approximation to find out the threshold voltage. The effect of high-k on various performance parameters of N-type DG-JLFET is explored. The comparative analysis has been carried out between conventional gate oxide, multi oxide and high-k oxide in terms of Drain Induced Barrier Lowering (DIBL), threshold voltage, figure of merit (ION/IOFF) and sub-threshold slope (SS). The high-k oxide has shown superlative performance as compared to others. The results are further analyzed for various device structures. The DG-JLFET with HfO2 exhibits excellent attainment by mitigating the Short Channel Effects (SCEs). The significant reduction in off current makes the device suitable for ultra-low power applications. There is a 61.9 % and 34.29 % improvement in the figure of merit and sub-threshold slope in the proposed device as compared to other devices. The simulation of DG-JLFET is carried out using the Silvaco TCAD tool.

Analysis of drain induced barrier lowering for junctionless double gate MOSFET using ferroelectric negative capacitance effect

&lt;abstract&gt; &lt;p&gt;We analyze the drain induced barrier lowering (DIBL) of a negative capacitance (NC) FET using a gate structure such as a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) for a junctionless double gate (JLDG) FET. NC FETs show negative DIBL characteristics according to the ferroelectric thickness. To elucidate the cause of such negative DIBL, the DIBLs are obtained by the second derivative method using the 2D potential distribution and drain current-gate voltage curve. The analytical DIBL model is also presented for easy observation of the DIBL of NC FET. It has been found that the results of this analytical DIBL model are very similar to those of the second derivative method. The results of this analytical DIBL model are also in good agreement with the results of TCAD. As a result, it was found that the negative DIBL phenomenon is caused by the change according to the drain voltage of the charge existing in the ferroelectric material. The negative DIBL phenomenon easily occurred as the ferroelectric thickness increased and the thickness of SiO&lt;sub&gt;2&lt;/sub&gt; used as an insulator decreases.&lt;/p&gt; &lt;/abstract&gt;

Performance Enhancement of Asymmetrical Double Gate Junctionless CMOS Inverter With 3-nm Critical Feature Size Using Charge Sheet

In this paper, after calibrating the models and parameters used in the simulations based on experimental data, by using the opposite doping in the channel and between the gates in an asymmetric double-gate junctionless (JL) transistor with the 3nm gate length, a charge sheet (CS) was created. The results showed that, due to creating CS in the middle of the channel, the horizontal electric field was increased, thus more major carriers were depleted from the middle of the channel. With the analysis of the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{I}_{\mathrm{ DS}} - \text{V}_{\mathrm{ GS}}$ </tex-math></inline-formula> diagrams at different temperatures, it was concluded that in the CS JL MOSFET, while the ON-state current is very close to compared that in the JL MOSFET (same structure without CS), the drain leakage current has decreased by around 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> . Furthermore, the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{I}_{\mathrm{ DS}} - \text{V}_{\mathrm{ DS}}$ </tex-math></inline-formula> diagram showed that the drain current in the CS JL MOSFET was much less affected by the drain voltage compared to that in the JL MOSFET. Also in AC analysis and at 1MHz frequency, by using CS the parasitic capacitances were reduced. Due to the improvement obtained in the presence of the charge sheet, the proposed structure was used in designing an inverter. The results showed that in the presence of the charge sheet, logical high input range, and logical low input range were increased, and also, noise margin low (NM <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</sub> ) and noise margin high (NM <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">H</sub> ) were improved.

A Novel Approach to Investigate Analog and Digital Circuit Applications of Silicon Junctionless-Double-Gate (JL-DG) MOSFETs

The double gate junctionless transistor (DG-JLT) has become the most promising device in sub nano-meter regime. DGJLT based circuits have improved performance and simpler fabrication than their inversion mode counterparts. This paper demonstrates the design of different analog and digital circuits using DGJLT. Amplifiers and inverters are the basic building block of electronic ICs. A MOS amplifier converts the variation of the gate to source voltage to a small current under transconductance and hence, the output voltage. A single-stage amplifier and differential amplifier have been designed with junctionless-double-gate (JL-DG) MOSFET. Trans-conductance, output voltage, and gain have been investigated using ATLAS 2D device simulator. The inverter is the primary logic gate that can be used to verify the device’s response in digital applications. Further, CMOS inverter have been designed using JL-DG MOSFET, and its performance parameters such as switching voltage, noise margin, and logic delay have been analyzed. A switching voltage of 0.43 V, noise margin of 0.265 V, and a delay of 19.18 psec have been obtained for the basic cell. CMOS inverter using JL-DG MOSFET at 20 nm channel length have prompted better performance results. Thus, The JL-DG MOSFET has a bright future in low-power analog and digital applications.

Improvements in FOMs and Thermal Effects of a III-V Compound Material Based Short-Channel Thin Film Junctionless Double Gate MOSFETs

Better figure of merits (FOMs) have been achieved by using III-V compound material based junctionless double gate metal-oxide semiconductor field-effect transistors (JL DG-MOSFETs), and a thorough analysis of the device’s performance over temperature has been performed using a highly N-doped GaAs-based JL DG-MOSFET using III-V compound material GaSb. GaSb, a compound material, is employed as the source material, which is well known for its greater mobility and injection velocity property with GaAs as the channel and drain materials, to obtain more output current and less leakage current due to the development of hetero structure (GaSb-GaAs) at the source-channel interface. The dielectric material HfO2 with a high k value is utilized to reduce the gate tunneling effects of electrons and enhance the control of the gate at the 20 nm channel length. Primary and auxiliary gates are taken to include ipact ionization on drain side for reducing the Subthreshold-swing. Numerous characteristics of a DG JLMOSFET, such as Id, SS, gm, TGF, Ion/Ioff, Cgs, and fT, GFP, TFP, GTFP are explored and compared with a silicon based material. The proposed structure shows an improved results comparing to the earlier model with Id of 117 mA, SS of 15.08 mV decade−1, gm of 0.62 A V−1, TGF of 38.8 V−1, Ion/Ioff ratio of 1.89 × 10 13, Cgs of 5.86 × 10 −16 F, fT of 2.05 × 10 15 Hz, GTFP of 1.81 × 10 17 Hz/V for the improvement of FOM in RF and DC analysis.

Analog/RF Performance of Triple Material Gate Stack-Graded Channel Double Gate-Junctionless Strained-silicon MOSFET with Fixed Charges

In this paper, analog/radio frequency (RF) electrical characteristics of triple material gate stack-graded channel double gate-Junctionless (TMGS-GCDG-JL) strained-Si (s-Si) MOSFET with fixed charge density is analyzed with the help of Sentaurus TCAD. By varying the various device parameters, the analog/RF performance of the proposed TMGS-GCDG-JL s-Si MOSFET is evaluated in terms of transconductance-generation-factor (TGF), early voltage, voltage gain, unity-power-gain frequency (fmax), unity-current-gain frequency (ft), and gain-transconductance frequency product (GTFP). The results confirm that the proposed TMGS-GCDG-JL s-Si MOSFET has superior analog/RF performance compared to gate stack-graded channel double gate-junctionless (GS-GCDG-JL) s-Si device. However, the proposed MOSFET has less transconductance and less output conductance when compared with the GS-GCDG-JL s-Si device in above threshold region, and reverse trend follows in sub-threshold region.

18nm n-channel and p-channel Dopingless Asymmetrical Junctionless DG-MOSFET: Low Power CMOS Based Digital and Memory Applications

In this paper, an 18nm dopingless asymmetrical junctionless (AJ) double gate (DG) MOSFET has been designed for suppressed short channel effects (SCEs) for low power applications. A desired ON and OFF state current ratio with subthreshold performance parameters under limit, is the major focus of the proposed transistor. Different sensitivity parameters of dopingless AJ DG MOSFET such as drain extension, length of gate overlapping and oxide thickness are compared with the AJ DG MOSFET with doped channel region. The ON-state current obtained is 3.80 x \({10}^{-6 }\)A/µm with reduced OFF-state leakage current up to1.37 x \({10}^{-17 }\)A/µm. The subthreshold slope (SS) and drain induced barrier lowering (DIBL) of the device obtained are 59.5 mV/decade and 10.5 mV/V respectively. Temperature analysis of proposed device at various temperature such as 250 K,300 K, 350 and 400 K shows a small variation in OFF-state current (< 15 %). Additionally, a p-channel AJ DG MOSFET along with n-channel AJ DG MOSFET are designed and their performance is evaluated for CMOS inverter circuit and 6T SRAM cell. All design and analysis have been done with a 2D/3D Visual TCAD device simulator.

Analysis of on-off current ratio in asymmetrical junctionless double gate MOSFET using high-k dielectric materials

&lt;span&gt;The variation of the on-off current ratio is investigated when the asymmetrical junctionless double gate MOSFET is fabricated as a SiO&lt;sub&gt;2&lt;/sub&gt;/high-k dielectric stacked gate oxide. The high dielectric materials have the advantage of reducing the short channel effect, but the rise of gate parasitic current due to the reduction of the band offset and the poor interface property with silicon has become a problem. To overcome this disadvantage, a stacked oxide film is used. The potential distributions are obtained from the Poission equation, and the threshold voltage is calculated from the second derivative method to obtain the on-current. As a result, this model agrees with the results from other papers. &lt;/span&gt;&lt;span&gt;The on-off current ratio is in proportion to the arithmetic average of the upper and lower high dielectric material thicknesses. The on-off current ratio of 10&lt;sup&gt;4&lt;/sup&gt; or less is shown for SiO&lt;sub&gt;2&lt;/sub&gt;, but the on-off current ratio for TiO&lt;sub&gt;2&lt;/sub&gt; (&lt;em&gt;k&lt;/em&gt;=80) increases to 10&lt;sup&gt;7&lt;/sup&gt; or more.&lt;/span&gt;

Effects of Hafnium Oxide on Short Channel Effects and DC Analysis for Double Gate Junctionless Transistors

Effects of Hafnium Oxide on Short Channel Effects and DC Analysis for Double Gate Junctionless Transistors

An analytical 2-D model of triple metal double gate graded channel junctionless MOSFET with hetero-dielectric gate oxide stack

In this paper, a two-dimensional analytical model of a laterally graded-channel triple-metal double-gate Junctionless Field Effect Transistor with hetero dielectric gate oxide stack consisting of SiO2 and HfO2 is derived. The model illustrates higher drive current and better performance against hazardous SCEs and HCEs in below 30 nm regime. Parabolic approximation method is used here to construct channel potentials and electric fields by solving 2-D Poisson's equation with applicable boundary conditions. The basic central and surface potentials as well as central and surface electric fields are being illustrated, Threshold voltage, DIBL, sub-threshold swing (SS) and a compact current model have also been deduced. These parameters clearly show the benefits of proposed graded-channel triple-metal double-gate structure with hetero-dielectric gate oxide stack. The device has reliability in low power applications because of its better Ion and Ioff control. Finally, the analytical model is validated with self-consistent numerical calculations to illustrate better performance of among available junctionless devices.

Design and Performance Analysis of Proposed Biosensor based on Double Gate Junctionless Transistor

Design and Performance Analysis of Proposed Biosensor based on Double Gate Junctionless Transistor

An Approach for Drain Current Modeling Including Quantum Mechanical Effects for a DMDG Junctionless Field Effect Nanowire Transistor

This paper presents the effects of quantum confinements on the surface potential, threshold voltage, drain current, transconductance, and drain conductance of a Dual Material Double Gate Junctionless Field Effect Nanowire Transistor (DMDG-JLFENT). The carrier energy quantization on the threshold voltage of a DMDG-JLFENT is modeled, and subsequently, other parameters like drain current were analytically presented. The QME considered here is obtained under the quantum confinement condition for an ultra-thin channel, i.e., below 10 nm of Si thickness. The threshold voltage shift due to QME can be used as a quantum correction term for compact modeling of junctionless transistors. The analytical model proposed for surface potential, threshold voltage, drain current, transconductance, and drain conductance were verified by TCAD 3-D quantum simulation results which makes it suitable for SPICE compact modeling.