Device Junction Temperature Research Articles

Selection Method of Test Pulse Width and Amplitude to Avoid Self-heating Effect of Power Devices

The objective of this study was to address the deviation of electrical parameters, which is caused by the self-temperature rise effect of power devices in electrical testing processes. The pulse width and amplitude of the device test were considered as the research object. The three-dimensional variation of the power, junction temperature, and pulse width of semiconductor power devices were investigated using the principle of electrical temperature measurement, and the three-dimensional variation surfaces of the power, junction temperature, and pulse width were established. A method for selecting the pulse width and amplitude of the test to avoid the self-temperature rise of the power device is proposed. This method uses cutting projection to obtain the characteristic curve of the pulse width and power change, and selects an appropriate two-dimensional region of the pulse width and power to avoid the self-temperature rise of the power device. Moreover, the proposed method can be used as a reference when selecting a pulse test method.

Time-Efficient Integrated Electrothermal Model for a 60-kW Three-Phase Bidirectional Synchronous DC–DC Converter

This article introduces an accurate and fast electrothermal model to calculate power loss and junction temperature of power electronic devices in a three-phase dc–dc converter, and to simulate converter dynamics during a simulated drive cycle. The proposed electrothermal model calculates power loss and junction temperature by representing the three-phase dc–dc converter dynamics within a drive cycle using a three-phase state-space average model. The three-phase state-space average model is modified to represent converter dynamics when one or two phases are off , in addition to the phase transition dynamics. The existing electrothermal models can either represent converter dynamics but are too slow for long simulations like drive cycles, or they reduce the simulation time at the expense of junction temperature accuracy. Furthermore, the existing electrothermal models in the literature are for inverters and single-phase dc–dc converters. The proposed electrothermal model combines the advantages of fast simulation time with accurate estimation of junction temperature. The power loss calculated by the proposed method is verified by a switching Simulink/PLECS model, and the mosfet temperature estimation is validated experimentally using a 60-kW three-phase bidirectional boost converter under steady-state conditions and a custom drive cycle. The efficiency of the three-phase converter is measured experimentally and compared with the efficiency calculations from the proposed electrothermal model.

Active Gate Delay Time Control of Si/SiC Hybrid Switch for Junction Temperature Balance Over a Wide Power Range

The optimal gate delay time control between the two internal devices to achieve excellent electrical and thermal performance of the Si/SiC hybrid switch is considerably affected by several factors and requires careful adjustment to suit the different operation conditions of power converters. However, the conventional gate control solution for the hybrid switch applies a fixed delay time to achieve the minimum switching loss at a specific load current, resulting in disparities in junction temperature of internal devices over a wide load range. This effectively reduces the safe operating area by risking one internal switch subjected to overrated junction temperature in a wide range operation with regard to power handling condition. To avoid such a serious risk of reliability degradation or thermal breakdown, a novel active gate delay time control strategy based on the electro-thermal coupling loss model is proposed. The gate delay time was dynamically adjusted and optimized according to the operation conditions of power converters so that the operation junction temperature difference of the two internal devices can be minimized. Experimental results demonstrate that the junction temperature of the hybrid switch decreases by 20 °C at 8-kW load condition and its maximum power handling capability increases by 18%, without compromising the power converter's efficiency in a 20 kHz Si/SiC hybrid switch-based dc/dc buck converter compared with the conventional approach.

FPGA-Based Device-Level Electro-Thermal Modeling of Floating Interleaved Boost Converter for Fuel Cell Hardware-in-the-Loop Applications

Floating interleaved boost converter (FIBC) is a promising topology of the dc/dc converters to interface the fuel cell with dc bus in a hybrid powertrain. For the efficient control development of power converters, the hardware-in-the-loop (HIL) simulation plays an important role. The accuracy of the real-time model determines the credibility of the HIL simulation. In order to take the power losses and thermal stress into account in the control development, the device-level real-time model is becoming popular in recent years, which can effectively produce device transient voltage and current waveforms, switching power dissipations, and thermal behaviors. In this paper, a device-level electro-thermal model of FIBC is proposed and developed using the field programmable gate array based real-time simulation technology. The FIBC network model can effectively be simulated with a 500-ns time step while producing the insulated-gate bipolar transistor transient switching waveforms authentically with a 5-ns resolution. The switching power losses can thus be estimated in real time and then used for the computation of the IGBT thermal behavior. Therefore, the device junction temperature can be evaluated in the real-time simulation. The accuracy of the proposed FIBC device-level model is validated by the reference model in the Saber offline simulation tool. At last, an embedded PI controller of FIBC is employed in the real-time experiments to verify the effectiveness of the developed model.

A Simplification Method for Power Device Thermal Modeling With Quantitative Error Analysis

To evaluate the reliability of power electronic systems, it is necessary to estimate the junction temperatures of power devices under periodic power loss profiles due to the fundamental-frequency current. However, a large number of periodic power loss profiles under long-term reliability evaluation (e.g., 1 year) are challenging to compute quickly. On the other hand, in order to improve computational efficiency, unvalidated simplified thermal analysis methods may impair the confidence of the reliability outcome. Therefore, this paper proposes an analytical model for power semiconductors with a compromise of the thermal estimation accuracy and computational efficiency. With the proposed model, it is indicated that minimum computation efforts can be obtained for thermal estimation under a maximum allowable error. The proposed method, thus, enables computation-efficient thermal stress analysis for power semiconductor devices with a preset modeling error. The effectiveness of the proposed method has been verified by simulations and experiments on a power electronic system with 1200-V/50-A insulated gate bipolar transistor (IGBT) modules.

Electroluminescence-Based Junction Temperature Measurement Approach for SiC Power MOSFETs

The measurement of the junction temperature of power semiconductor devices during operation is highly relevant for efficient power electronic applications. This paper presents a novel galvanic isolated sensing approach for the online junction temperature measurement of a silicon carbide (SiC) mosfet . It is based on the temperature-dependent changes in the spectrum of the light emission from the body diode of the SiC mosfet . The spectrum exhibits two characteristic peaks at roughly 380 nm and around 480 nm. The first peak's intensity increases with rising temperature, whereas the other decreases. Consequently, the junction temperature can be derived from the ratio of the filtered intensities of those two wavelength regions. The proposed method is studied on the basis of a virtual experiment and experimentally validated by means of static characterization and dynamic double pulse measurement.

Performance Evaluation of a Loop Thermosyphon-Based Heatsink for High-Power SiC-Based Converter Applications

Thermal management system (TMS) of a power converter directly dictates the available power rating, power density, semiconductor module reliability, and its operating lifetime. For the latest-generation wide bandgap (WBG) semiconductor device-based converters, it is challenging to extract the generated heat from the devices due to smaller die area as compared to its silicon (Si) counterparts. In this paper, the thermal performance of a new loop thermosiphon-based TMS for silicon carbide (SiC) semiconductor device-based power conversion system is presented. The working principle and design of the TMS are shown, and the performance of the designed TMS in both transient and steady-state conditions of power dissipation is evaluated. Furthermore, an accurate thermoelectrical model of the TMS is presented, and the circuit parameters are quantified by experimental results. This analysis helps to estimate the device junction temperature in real time during converter operation. Moreover, detailed simulations are carried out with the derived TMS thermal model to evaluate its performance at low fundamental frequencies at rated currents. The experimental results and the simulation studies indicate that the TMS offers a low thermal resistance and can extract a large amount of heat without increasing the device junction temperatures beyond their rated values. Furthermore, the designed TMS is able to maintain the junction temperature ripples at low fundamental frequencies within small values, which helps to increase the lifetime of the power modules significantly, as compared to conventional heatsinks.

Automated Heatsink Optimization for Air-Cooled Power Semiconductor Modules

Heatsink design is critical for power density and reliability enhancement of power semiconductor modules. In this letter, an automated design and optimization methodology for air-cooled heatsinks are proposed based on genetic algorithm and finite element analysis. While the genetic algorithm generates a population of candidates with complex heatsink cross-section geometry in each iteration, finite element analysis is used to evaluate the fitness function of individual heatsink, i.e., junction temperature of semiconductor devices. With the rule of “survival of the fittest,” the proposed methodology eventually converges to an optimum heatsink design with the lowest device junction temperature. The optimized heatsink is fabricated through three-dimensional printing technology for thermal performance evaluation. Simulation and experimental evaluations have been conducted based on a 50-kW three-phase air-cooled inverter with the fabricated heatsinks. The comparative evaluation results show that the optimized heatsink is superior over a customized solution by 27% less in size and 6% lower in junction temperature.

A Viable Mission Profile Emulator for Power Modules in Modular Multilevel Converters

Various methods have been presented in the past to emulate the electrical behavior of modular multilevel converters (MMCs). To meet the demands for the reliability aspect study of MMCs, this paper proposes a viable setup to emulate the thermal behavior and to investigate its feasibility for reliability testing and thermal model validation of the power modules in the MMC. The proposed mission profile emulator has three distinctive features: 1) capable of emulating and measuring the thermal stresses of power modules; 2) capable of implementing practical switching profile as a full-scale MMC; and 3) having significantly reduced requirement for dc power supply compared to existing setups used for electrical studies. Theoretical discussions, and simulations as well as the experimental results are presented to demonstrate the capability of the mission profile emulator both electrically and thermally. Moreover, this paper is accompanied by a video demonstrating how to measure the junction temperature of the power devices using the optical fiber and the thermal camera.

Imbalance Current Analysis and Its Suppression Methodology for Parallel SiC MOSFETs with Aid of a Differential Mode Choke

Parallel connection of silicon carbide (SiC) MOSFETs is a cost-effective solution for high-capacity power converters. However, transient imbalance current, during turn- on and - off processes, challenges the safety and stability of parallel SiC MOSFETs. In this paper, considering the impact factors of device parameters, circuit parasitics, and junction temperatures, in-depth mathematical models are created to reveal the electrothermal mechanisms of the imbalance current. Moreover, with the incorporation of a differential mode choke (DMC), an effective approach is proposed to suppress the imbalance current among parallel SiC MOSFETs. Physics concepts, operation principles, and design guidelines of the DMC-based suppression method are fully presented. Besides, to reduce the equivalent leakage inductance and equivalent parallel capacitance of the DMC, winding patterns of the DMC are comparatively studied and optimized to suppress turn- off over-voltage and switching ringing. Concerning the influence of winding patterns, load currents, gate resistances, and junction temperatures, experimental results are comprehensively demonstrated to confirm the validity of theoretical models and the function of the proposed DMC-based suppression method. It is turned out the low-cost DMC is easy to design and utilize without complex feedback circuits or control schemes, which is a cost-effective component to guarantee consistent and synchronous on–off trajectories of parallel SiC MOSFETs.

Gate Control Optimization of Si/SiC Hybrid Switch for Junction Temperature Balance and Power Loss Reduction

The hybrid switch concept of paralleling a higher-current main Si IGBT and a lower-current auxiliary SiC mosfet offers an improved cost/performance tradeoff in power converters. Currently, the gate control strategy of these two internal devices emphasizes on minimizing the total power loss, and is referred to as the efficiency control mode in this paper. However, there is a serious risk of overheating and reliability degradation of the SiC mosfet if solely relying on this control strategy. In this paper, we propose a new method of gate control optimization, referred to as the thermal balance control mode, to keep the junction temperature of both devices within the specified temperature range, and to minimize the total power loss simultaneously. We first investigate the dependency of the hybrid switch switching losses on the gate control pattern both theoretically and experimentally. We then extensively study control optimization in these two distinct control modes in a dc–dc boost converter. It is found that the thermal balance control mode can achieve almost the same total power loss as the efficiency control mode, but much lower and more balanced junction temperatures of the two internal devices. Experimental results demonstrate that the Si/SiC hybrid switch in an optimal thermal balance control mode can achieve a 163% higher power handling capability in the 20-kHz boost converter or four times higher switching frequency in the 4-kW boost converter than a single IGBT solution with hard switching condition, and yet a considerably lower component cost than a single SiC mosfet solution in the boost converter.

Reliability modelling and analysis on MMC for VSC‐HVDC by considering the press‐pack IGBT and capacitors failure

Modular multi-level converter (MMC) with press-packing IGBT devices is the popular and key equipment of VSC-HVDC system, its reliability is directly related to the equipment safe operation. However, it is difficult to analyse the reliability using the failure statistical approach due to less fault data. In order to improve the reliability analyses accuracy, it is necessary to use the physical failure method by considering the main components fatigue failure mode. The reliability analysis models are presented for the MMC sub-module with the press-packing IGBT device and metallised film capacitors. First, based on the MMC-HVDC simulation model, the losses and the junction temperatures of the IGBT devices were derived by the temperature field model, which the failure rates can be calculated. Furthermore, based the corrosion failure mode, the failure rate calculation of the metallised film capacitor was investigated using the voltage stress and thermal stress, the reliability calculation of the MMC sub-module was presented by combining the main components failure rates. Finally, the reliability of the VSC-HVDC based MMC was also presented with the different operation mode. The achievement is helpful to assess and improve the reliability of the VSC-HVDC.

Power electronics thermal solutions using thermally conductive polyimide films

Increased adoption of hybrid and electrical vehicles as well as renewable energy systems are driving the innovation in power module packaging. Thermal substrate, one of the major components of power modules, is not an exception, and technological advancements are necessary to meet increased reliability requirements. DuPont has developed a thermally conductive polymer film that provides very low thermal resistance and very high insulation. The film can be bonded to conductive and thick metallic layers and this polymer equivalent of DBC shows very high reliability in addition to high performance characteristics. Electrically insulating layers within a power electronics module are critical for separating circuitry from thermal management layers. Electrical insulating substrates typically used in power electronics modules utilize a ceramic layer, comprised most commonly of either Al2O3, AlN, or Si3N4. Thin Cu layers are bonded to either side of the substrate using a direct bond Cu (DBC) or active metal brazing (AMB) process. These processes involve bonding metallization layers to both sides of the ceramic at a high temperature as bonding to only one side would cause deformation during the cooling phase. Typical metal thickness bonded to either side of the ceramic is about 0.3–0.6 mm as the high temperature manufacturing process does not allow very thick metals to be bonded and this limits the heat spreading capability of the thermal substrate. DuPont's new Temprion™ Organic Direct Bond Copper (ODBC) address aforementioned problems, increasing thermal durability and reliability as well as enabling system layer suppression. Temprion™ ODBC's dielectric layer will absorb thermo-mechanical stress from the metals due to CTE mismatch, dramatically improving durability of the system. In addition, various kinds of metals including Cu and Al can be easily bonded to Temprion™ DB films through simple process. There are no thickness limitations on bonding metal sheets and metal attached at the bottom can be used as an integrated heat sink/baseplate. Al2O3 and Si3N4-based substrates were utilized as a baseline for reliability comparison with the DuPont substrates. The industry-standard substrates in used in this study have a thickness of 0.3 and 0.8 mm for the Cu metallization layers and 0.38 and 0.32 mm for the insulating layer respectively for Al2O3 an Si3N4 insulators. DuPont ODBC substrates were fabricated by attaching a polyimide layer to a layer of 0.8-mm-thick Cu. The polyimide and bottom Cu layer cross-sectional footprints are both 50.8 mm × 50.8 mm. The corners of both layers were filleted with various radii (0.5, 1.0, 2.0, and reversed 2.0 mm) to explore the impact of different stress concentrations between the metallization and insulating layers. The top Cu metallization was inset 2.0 mm from the perimeter of the electrically-insulating substrate and bottom Cu metallization.10 samples each of the DuPont ODBC and industry Al2O3 substrates were placed in a thermal shock chamber and cycled between temperature extremes of −40°C and 200°C. Substrates were inspected every 1000 cycles. After 5000 cycles, the ODBC substrates experienced no hipot failures, but preliminary edge delamination was visually observed. Al2O3 substrates all failed after 50 thermal cycles.Five DuPont ODBC samples were placed in a thermal chamber and subjected to an elevated temperature of 175°C. After 2000 hours, no hipot failures were observed, but edge delamination was again observed.Five DuPont ODBC samples were attached to a cold plate with Kapton tape. Heater cartridges were attached to the top of the substrates with Kapton tape and thermocouples were placed in several locations through the package. The heater cartridges were alternated between on and off states to allow for the substrates to cycle between −40°C and +200°C. While the change between the maximum and minimum temperatures is smaller for the power cycling test compared to the thermal cycling test, the heater cartridge and cold plate create a thermal gradient within the samples that is not possible with passive thermal cycling. After 2000 hrs cycles of testing, no hipot failures or edge delamination have been observed. Herein we show that the DuPont ODBC substrate design is a promising alternative to traditional industry substrates based on ceramic insulators. The reliability of the substrate design has been demonstrated under several thermomechanical accelerated tests and the electrical and thermal performance has been measured. Future work will include reliability comparisons to other industry substrates, including thermal shock testing of substrates with HPS, AlN, and Si3N4 ceramic layers. Thermal models will correlate thermal resistance values measured by the transient thermal tester and compare the ODBC substrate performance to industry substrates within a commercialized power electronics module. The modeling will also optimize the thickness of the metallization layers within the ODBC substrates to minimize the junction temperature of the switching devices.

Thermal Characterization of Quasi-Vertical GaAs Schottky Diodes Integrated on Silicon Using Thermoreflectance and Electrical Transient Measurements

Thermal management and design have been understood, for many years, as critical factors in the implementation of submillimeter-wave Schottky-diode-based circuits and instruments. Removal of heat is particularly important for frequency multipliers, as these circuits generally exhibit low-to-modest conversion efficiencies, and are usually driven with high-power sources to achieve usable output power in the submillimeter-wave region of the spectrum. Elevated diode junction temperature due to inadequate heat sinking is known to degrade performance, accelerate aging effects (for example, due to electromigration, ohmic contact deterioration, or thermally-induced stress), and can ultimately lead to device failure. The relatively-low thermal conductivity of GaAs (the predominant material technology for submillimeter-wave diodes), coupled with restrictions on diode anode size and geometry needed to minimize parasitics and achieve the device impedances required for high-frequency operation, present significant challenges and trade-offs between electrical and thermal designs of these devices. Recognition that heating is a major factor limiting efficiency and output power has prompted a number of approaches to mitigate excessive temperature rise in the junction of planar Schottky diodes, including the use of AlN or diamond as low-loss substrates that act as heat spreaders. A new diode topology, based on a quasi-vertical geometry that is realized through heterogeneous integration of GaAs with high-resistivity silicon, was recently developed at the University of Virginia for submillimeter-wave applications. Unlike planar diodes, the device structure of the quasi-vertical diode consists of a metal contact that underlies the diode's anode and epitaxial mesa, thus providing a large-area ohmic cathode contact that also serves as an integrated heat sink. Measurement of high-efficiency multipliers based on this technology suggest the quasi-vertical architecture provides an effective approach for heat removal and thermal management in Schottky diodes. This paper presents the first results reporting thermal performances of terahertz quasi-vertical GaAs Schottky diodes integrated on silicon. The devices are characterized using a thermoreflectance measurement technique, a method based on the change in refractive index, and therefore surface reflectivity, with changes in temperature. Heating and cooling temperature profiles and 2-D temperature maps are obtained for 3.5 micron and 5.5 micron diameter diodes. From these measurements, the device thermal resistances, junction temperatures, and thermal time-constants are extracted. Equivalent thermal circuit and finite element models are developed to study the device geometry, and extract material thermal parameters. The devices are also characterized using an electrical transient method, and the temperature and cooling transients found from this technique are found to be comparable to those obtained from thermoreflectance measurements. The quasi-vertical diodes studied in this work are shown to demonstrate a faster transient thermal response compared to flip-chip bonded terahertz diodes reported in the literature.

Method of junction temperature estimation and over temperature protection used for electric vehicle's IGBT power modules

Abstracts High-power insulated gate bipolar transistor (IGBT) modules are widely used in power electronic systems, their system reliability is received more and more attention. The junction temperature of power devices is an important factor affecting reliability of power electronic systems. For electric vehicle applications, this paper proposes a method of junction temperature estimation and over temperature protection is used for electric vehicle's IGBT power modules. According to two junction temperature estimation methods, one is based on the thermal impedance model of IGBT modules, and the other is based on the relationship between the negative temperature coefficient (NTC) thermistor temperature and the chip temperature inside modules, two estimated junction temperatures can be obtained. Under different working conditions, the two estimated junction temperature ratios are adjusted to obtain an optimal estimated junction temperature. Based on the junction temperature estimation, several temperature thresholds are set. When the temperature reaches the threshold value, the motor drive control is used to perform effective over temperature protection to prevent the IGBT modules of the electric vehicle inverter from being ineffective due to the excessive junction temperature and resulting in the loss of vehicle power.

Ambient Temperature and Self-Heating Scaling Laws for Materials With Temperature-Dependent Thermal Conductivity

Two of the primary variables affecting junction temperature of semiconductor devices are the self-heating due to internal power dissipation within the device and the device's base (or ambient) temperature. For materials with temperature-independent material properties, the junction temperature is a linear function of these two variables, which allows for simple “scaling” of the junction temperature for arbitrary dissipation and/or base temperatures. In materials with temperature-dependent material properties, however, the relationship between junction temperature and either variable is nonlinear. The scaling law between junction temperature and dissipated power and base temperature for materials with temperature-dependent material properties are developed in this work. This scaling law allows for fast computation of junction temperature for any values of power dissipation and/or base temperature given the junction temperature for one specific instance of power dissipation and base temperature and hence may find applicability in fast electrothermal solvers.

Real-Time Junction Temperature Sensing for Silicon Carbide MOSFET With Different Gate Drive Topologies and Different Operating Conditions

The switching transient properties from the switching power semiconductor gate side are sensitive to the device's junction temperature ( $T_{j}$ ). Real-time $T_{j}$ sensing methods based on gate drive switching transient properties have been investigated on silicon MOSFET and silicon IGBT, with a conventional push–pull-type gate drive, under fixed dc-bus voltage. In this paper, this method is applied to silicon-carbide (SiC) MOSFET. The $T_{j}$ sensing methods are evaluated with different types of gate drive topologies. By implementing the SiC MOSFETs into an H-bridge inverter, the effect of dc-bus voltage for the $T_{j}$ sensing method is investigated. Different “gate drive−semiconductor” dynamic models are built, including gate drive output power stage, gate drive parasitics, SiC MOSFET intrinsic parameters, and PCB parasitics. Experimental results are compared with circuit LTSpice model simulation. The device vertical temperature contours are evaluated. Suitable circuitry for $T_{j}$ sensitivity extraction is provided.

Design of the airflow passage structure for improving the thermal performance of the power conversion system

In order to operate a Power conversion system (PCS) reliably, which is used for solar or wind power generation and energy storage systems, a design engineer of a PCS must evaluate that the junction temperature of power semiconductor devices, such as an Insulatedgate bipolar transistor (IGBT) module, meets the design criteria in the cooling design stage. An engineer must have evaluation procedure to design the airflow passage structure of a PCS in a way that the heat generated from inside of the system can be effectively exhausted externally. This study investigated the thermal performance of a PCS for four different airflow passage structures using the airflow rate of the heat sink attached to the IGBT module as an evaluation index. Out of the suggested airflow passage structures, the structure using the upper supply-lower exhaust type without the cooling fan for the reactor, which forms the air curtain around the airflow passage guide of the IGBT module and the louver of the maintenance door, has been found to perform the best thermal performance. In this design, the airflow rate of the heat sink was approximately 14 % larger than the required rate, with the junction temperature of the IGBT module of 132.2 °C, which satisfied the cooling design criteria. When the ventilation area of the supply is increased by approximately 2.3 times and the thickness of the filter reduced by 10 mm, the airflow rate of the heat sink can reach up to 700.4 m3hr-1, and in this case, the design criteria of the IGBT module can be satisfied even in an overload condition of 106.7 % of the rated load.

Experimental study on the influence of junction temperature on the relationship between IGBT switching energy loss and device current

Accurate determination of power losses in semiconductor devices is important for optimal design and reliable operation of a power converter. The switching loss is an important component of the total device loss in an insulated-gate bipolar transistor (IGBT) in a voltage source inverter. The objective here is to study experimentally the influence of junction temperature on the turn-on switching energy loss Eon and turn-off switching energy loss Eoff. More specifically Eon and Eoff are both related to device current Ic; the influence of junction temperature on the relationship between Eon and Ic and that between Eoff and Ic is studied. As the operating environmental conditions and load conditions of power converter vary widely, a wide range of junction temperatures between −35°C and +125°C is considered here. The experimental data enable precise determination of the switching loss in each device in a high-power converter at any practical operating condition. This leads to precise estimation of total device loss and optimal thermal design of the converter. This further helps off-line and/or on-line estimation of device junction temperatures required for study of thermal cycles and reliability.

Increasing the reliability of wind turbines using condition monitoring of semiconductor devices: a review

The majority of electrical failures in wind turbines occur in the generator-side semiconductor devices. This is due to temperature swings affecting the layers of insulated-gate bipolar transistors in different ways; these effects are aggravated by the variation of wind speed. The implementation of accurate on-line condition monitoring mainly relies on on-line tracking of the temperature variation of components. The maximum temperature stress is observed at the junction terminal of the devices, which cannot be easily measured. Additionally, it is difficult to track the exact dynamic of temperature due to the slow response of sensors. Thus, several methods have been presented in the technical literature to estimate the junction temperature of the semiconductor devices. Each method has merits and disadvantages in terms of accuracy and complexity, as failure mechanisms have their own effects on the variation of junction temperature and some or all of the electrical parameters. Therefore, detection algorithms have to determine the root cause of the temperature variation. This study comparatively reviews the condition monitoring methods presented so far and gives directions on the future steps that should be addressed by research in this area.