Abstract
To evaluate the reliability of power electronic systems, it is necessary to estimate the junction temperatures of power devices under periodic power loss profiles due to the fundamental-frequency current. However, a large number of periodic power loss profiles under long-term reliability evaluation (e.g., 1 year) are challenging to compute quickly. On the other hand, in order to improve computational efficiency, unvalidated simplified thermal analysis methods may impair the confidence of the reliability outcome. Therefore, this paper proposes an analytical model for power semiconductors with a compromise of the thermal estimation accuracy and computational efficiency. With the proposed model, it is indicated that minimum computation efforts can be obtained for thermal estimation under a maximum allowable error. The proposed method, thus, enables computation-efficient thermal stress analysis for power semiconductor devices with a preset modeling error. The effectiveness of the proposed method has been verified by simulations and experiments on a power electronic system with 1200-V/50-A insulated gate bipolar transistor (IGBT) modules.
Published Version
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