Junction Temperature Rise Research Articles

Improved Nonlinear Self-Heating Compact Modeling in SiGe HBTs Using Mextram

Accurate modeling of self-heating (SH) induced junction temperature rise is crucial for circuit design at high current densities required for high speed and high gain, as well as for reliability, as most degradations worsen at higher temperatures. For relatively lower power, the junction temperature rise (Trise) is typically modeled as a linear function of the dissipated power (Pdiss), with the slope being a parameter named thermal resistance (Rth), which can be further modeled as a function of ambient temperature (Tamb).In Mextram, this was the case until the recent implementation of the nonlinear SH model of [1]-[4] in Mextram 505.4 to improve modeling for high-power applications [5] [6]. A notable feature of the Mextram nonlinear SH model implementation is that it uses the same model parameters as its linear SH model, i.e., the low power Rth at reference temperature, rth, and the material thermal conductivity temperature coefficient ath used to describe the Tamb dependence of the linear SH Rth. In the nonlinear SH model, the same ath is used for Pdiss dependence of the effective Rth.Theoretically, if ath is already physical, one can simply turn on the nonlinear SH switch for improved modeling at higher collector current (IC) and collector-emitter voltage (VCE). The key to this simplicity lies in the specific form of the nonlinear functional dependence of Trise on Tamb and Pdiss derived by solving the nonlinear heat diffusion equation using the Kirchhoff transformation [7].In practice, however, retuning these two parameters with high power data is beneficial for better overall fitting, particularly over multiple ambient temperatures. Fitting a larger power range at multiple ambient temperatures can still be challenging, due to the presence of multiple materials with different thermal conductivity temperature coefficients in the heat flow path and heat dissipation through multiple paths, e.g., from metallization in addition to substrate.To provide flexibility in silicon data fitting and extend the model's capability to a wider ambient temperature range and power range, we present an additional semi-empirical model. By deriving the slope of Trise versus Pdiss in the single material single path model problem, we show that it is only a function of the junction temperature Tjunc=Trise+Tamb, which is behind the ability of the model to use only two parameters for both Tamb and Pdiss variation.We propose a semi-empirical modification of the Trise versus Pdiss slope behavior, similar to the low-temperature CMOS measurement-based model in [8] and [9], which has the same issue of having a Tjunc-dependent Trise vs Pdiss slope, but an easier functional form for modification to provide flexibility in better fitting high power region over a wider range of ambient temperature. Our model construction ensures that the low Pdiss behavior is guaranteed to be the same as existing Mextram SH models.Figs. 1-3 show the modeling results of IC-VCE at various base-emitter voltages (VBEs) for a SiGe HBT at -25, 25, 75, and 125°C using 1) Mextram's default linear SH model; 2) Mextram 505.4's nonlinear SH model; and 3) the proposed wide power and temperature range nonlinear SH model. The new model shows the best overall fitting.In the full paper, we will also present results obtained using the nonlinear SH model used in HICUM L2 [10], where the effective Rth modeled as a linear or nonlinear function of Tjunc, and results obtained by implementing the model of [9]. We will make comparisons of the various models and provide best practice recommendations.[1] W. B. Joyce, SSE, vol. 18, pp. 321-322, 1975.[2] K. Poulton et al., JSSC, vol. 27, no. 10, pp. 1379-1387, 1992.[3] B. Yeats, Dig. GaAs IC symposium, pp. 59-62, 1999.[4] J. C. J. Paasschens et al., BCTM, pp. 96-99, 2004.[5] G. Niu et al., The Mextram Bipolar Transistor Model Version 505.4.0, 2023.[6] M. Willemsen, AKB-Workshop, 2023.[7] G. R. Kirchhoff, Vorlesungen über die Theorie der Wärme, 1894.[8] K. Triantopoulos et al., TED, vol. 66, no. 8, pp. 3498-3505, 2019.[9] G. Ghibaudo et al., SSE, vol. 192, article 108265, 2022.[10] M. Schroter, HICUM/L2 Technical documentation of model version 3.0.0, 2020. Figure 1

BeO in epoxy composites as TIM for high-power LED packages

Beryllium oxide (BeO)-filled epoxy composite was prepared and used as a thermal interface material (TIM) in light-emitting diode (LED) packages. The filler percentages influenced on changing thermal and optical behaviour of LED at various driving currents. An improvement of 14.36% in thermal conductivity was recorded from that of neat epoxy. The lowest total thermal resistance of 10.75 K/W ( Rth) and rise in junction temperature ( Tj) of 3.1°C were recorded at 100 mA driving current for 50 wt-% BeO-filled TIM attached LED followed by an improved optical output and lowered correlated colour temperature values (3466 K). Thermal imaging infra-red imaging analysis also supported the observation of reduced Tj and Rth values from transient analysis and indicated lower chip surface temperature ( Ts) at all driving currents.

Transient thermal 2D FEM analysis of SiC MOSFET in short-circuit operation including high-temperature material laws and phase transition of aluminum source electrode

Understanding the electrothermal behavior of SiC MOSFET power devices under extreme operation conditions, such as short circuits, is crucial for their application certification. However, simulating short circuits in electronic components is challenging due to the necessity of a comprehensive thermal and electrical Multiphysics model that incorporates material laws and respects elevated temperatures with broad ranges. It is also needed to model the melting of the topside Al electrode. The paper presents for the first time a 2D electrothermal FEM that simulates the thermodynamic behavior of SiC MOSFET at high temperatures transistors under short-circuit conditions, including wide-range temperature-dependent material property laws. This work models the Al phase transition by considering the apparent heat capacity method and including the latent heat absorbed during the Al solid-liquid phase change (PC). The geometric accuracy of this study provides significant added values compared to existing 1D models. It was deduced that including the temperature-dependent material laws highly impacted the results. The rise in SiC junction temperature led to a delay in the onset of Al melting. It also impacted the progression manner of the Al melting process after the formation of new melting fronts.

Copper-Wire Stress Buffers for Extending Lifetime of Double-Sided Bidirectional SiC Modules

The mismatch of thermal expansion coefficients causes tremendous thermo-mechanical stress in die attachment of double-sided bi-directional modules (BMs), thus reducing the reliability of the module. The thermo-mechanical reliability of a double-sided power module is the most critical issue, which needs to be addressed. People proposed ways to improve the reliability by reducing the CTE mismatches using such as Moly spacer instead of copper or junction temperature rise using high conductive spacer. This work first proposed a composite buffer, namely copper-wire-spacer (CWS), with low elastic modulus, capable of reducing thermo-mechanical stress by >50%. The lifetime of the double-sided BM with the CWS buffer is 40.0% and 42.9% longer than that with the conventional solid copper buffer, and is only 6.67% and 6.25% shorter than that with the moly buffer under the thermal shocking tests and the power cycling tests, respectively. The novel method of reducing the elastic modulus of the spacer could be a novel and good concept to reduce the thermo-mechanical stresses as well as improving the reliability of double-sided power modules. It can provide new guidance to design and packaging reliable double-sided power modules.

Fabrication and Performance of 300-mm Wafer-Scale Silicon Microchannel Cooler

This paper describes the design, fabrication, and thermal performance of 300 mm diameter wafer-scale Si microchannel coolers that demonstrated a junction temperature rise of less than 18°C when dissipating about 14 kW of power. A thermal test wafer, which included hot-spot regions to mimic high-power compute cores, was attached to the wafer-scale microchannel cooler with Pb-Sn solder. Glass manifold layers were attached to the microchannel wafer using a frit material. The average apparent heat transfer coefficient, h <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">app</sub> , was about 104,000 W/(K-m <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ).

Influence of extended surface area of heatsink on heat transfer: design and analysis

PurposeLight emitting diode (LED) has been the best resource for commercial and industrial lighting applications. However, thermal management in high power LEDs is a major challenge in which the thermal resistance (Rth) and rise in junction temperature (TJ) are critical parameters. The purpose of this work is to evaluate the Rth and Tj of the LED attached with the modified heat transfer area of the heatsink to improve thermal management.Design/methodology/approachThis paper deals with the design of metal substrate for heatsink applications where the surface area of the heatsink is modified. Numerical simulation on heat distribution proved the influence of the design aspects and surface area of heatsink.FindingsTJ was low for outward step design when compared to flat heatsink design (ΔT ∼ 38°C) because of increase in surface area from 1,550 mm2 (flat) to 3,076 mm2 (outward step). On comparison with inward step geometry, the TJ value was low for outward step configuration (ΔTJ ∼ 6.6°C), which is because of efficient heat transfer mechanism with outward step design. The observed results showed that outward step design performs well for LED testing by reducing both Rth and TJ for different driving currents.Originality/valueThis work is authors’ own design and also has the originality for the targeted application. To the best of the authors’ knowledge, the proposed design has not been tried before in the electronic or LED applications.

Performance Enhancement Method for Power Electronic Switch in Hybrid DC Circuit Breaker Based on Partial Precooling

Insufficient current capability is the most serious problem faced by power electronic devices in hybrid dc circuit breaker (HCB), where the junction temperature rise is the main restriction. This letter proposes a novel performance enhancement method for power electronic switch in HCB based on partial precooling. By applying thermoelectric cooling technology, the temperature of power electronic devices and their surrounding region can be reduced in advance in the steady state of the HCB, allowing the devices to achieve superior current performance. Then, a 4.5 kV power electronic switch module prototype with a low-cost integrated precooling unit was developed, which can provide a temperature drop of 15 °C for the power electronic device within, resulting in approximately 10% improvement in current performance.

A Temperature-Dependent Analytical Model of SiC MOSFET Short-Circuit Behavior Considering Parasitic Parameters

The superior electrical and thermal characteristics of silicon carbide (SiC) MOSFETs bring major challenges to its short-circuit reliability. To fully understand its short-circuit mechanism, estimate its safe operating area, and provide guidance for circuit design, it is crucial to establish a theoretical model to quantize the relationship between circuit parameters and short-circuit behavior of SiC MOSFETs. A temperature-dependent analytical model considering the parasitic inductances, nonlinear junction capacitances, and temperature dependence of the channel current is proposed in this article, which uses only the parameters in the datasheet or provided by manufacturers. The proposed model is established based on the analysis for each short-circuit stage in both single-device configuration and half-bridge configuration, and the quantitatively analytical results of the transient short-circuit waveforms, energy loss, and junction temperature rise can be calculated by solving the model. The accuracy of the analytical model is verified by comparing the analytical results with the experimental results. Furthermore, the effects of varied parameters on the short-circuit behavior are evaluated by the proposed analytical model. And the corresponding circuit design guidance for higher short-circuit reliability is given.

Case-embedded cooling for high heat flux microwave multi-chip array

• A case-embedded cooling is developed for microwave multi-chip module. • An analytical model is proposed to calculate thermal resistance. • The application range of the embedded cooling is determined. • A thermal test vehicle composed of 4 × 4 chip array is manufactured. • The accuracy of the model is verified by 3D simulation and experiment. This work proposes a case-embedded cooling (CECool) for microwave multi-chip module and theoretically studies its cooling capacity based on an improved analytical model. In this solution, the microfluidic cooling is integrated inside the case of the module to shorten the path of heat transfer. The model is used to calculate the thermal resistance from the chip to the coolant. The accuracy of the model is improved by setting the thermal diffusion angle to vary with the difference in thermal conductivities between the materials, which is validated by 3D finite-element-method simulation. Thermal performance of the remote cooling approach is studied first to help determine the application range of the CECool. By optimizing the materials and the microchannel, the thermal resistance of the CECool can be reduced to 5.7 °Cmm 2 /W. It is possible to increase the maximum tolerant heat flux to 1300 W/cm 2 by enhancing the microfluidic cooling and choosing the chip type, meanwhile keeping the rise of junction temperature below 60 °C. A thermal test vehicle composed of 4 × 4 chip array is manufactured for demonstration. The accuracy of the model is verified by the experiment at 471 W/cm 2 . The maximum error is only 5.4%.

Electromagnetic Simulation and Realization of MCM GaAs MMICs Based Packaging for High Gain (40 dB) and High-Power (33dBm) Transmitter Applications

This paper details the development of high thermal conductivity (395 W/mK) metal package which is suitable for high-gain and high-power multi-chip modules (MCM). This package is designed using thermal analysis data to meet the long-term reliability. Thermal modeling was done to estimate the thermal resistance and design of package made to minimize the thermal resistance in the heat dissipation path. It is a dual cavity structure MCM suitable for packaging GaAs-based MMICs working up to Ku-Band. This is a two-cavity package with dimensions 17.2 mm×10 mm×3.5 mm and they are internally separated cavities to handle the high gain and power, and the same package 3D EM simulation is done in CST studio 2016. This modeled package is optimized and fabricated by using copper material to meet the thermal management requirements of a power amplifier operated in CW mode. The S-parameter measurements were carried out over broadband also but considered over 6–18 GHz and test parameters resulted in typical S21 of 40 dB, S11 of 10 dB, S22 of 5 dB, and output power of 33 dBm. Thermal analysis is carried out using thermalyze software for analyzing the rise in junction temperature during DC biasing conditions and to calculate the necessity of junction cooling to get the highest output power. Temperatures at three stages are 100.13, 99.85 and 83.38 °C with the base plate maintained at a constant temperature of 60 °C. Further, studies carried out on different base materials for good heat flow and CTE match with GaAs dies as copper tungsten and copper–molybdenum copper.

A Comparison of the Short Circuit Performance of 650 V SiC Planar MOSFETs, Trench MOSFETs and Cascode JFETs

Short circuits that occur in power converters put the power semiconductor devices under considerable electrothermal stress. The electrothermal stress causes a rise in junction temperature and ultimately device failure if the thermal limits of the device are exceeded. The device ruggedness under short circuit conditions is quantified by the short circuit withstand time (SCWT), which is the maximum duration the power device can dissipate the short circuit energy without failure. SiC MOSFETs are known to have reduced short circuit capability compared to comparatively rated silicon MOSFETs and IGBTs due to higher thermal impedance and reduced gate oxide robustness. In this paper, 650V rated SiC planar MOSFETs, Trench MOSFETs and Cascode JFETs have been subjected to short circuits with initial junction temperatures of 25°C, 75°C and 150°C. The results show the peak SC energy density (in mJ/mm2) has a negative temperature coefficient for the Planar and Trench MOSFETs and is temperature independent for the Cascode JFET. The SCWT reduces with initial junction temperature for the SiC Planar and Trench MOSFET while showing less temperature dependency in the SiC Cascode JFET. The SiC Trench MOSFET demonstrates the highest SCWT although all devices show reduced SCWT compared to similarly rated silicon MOSFETs and IGBTs.

Electroless Ni–B sealing on nanoporous anodic aluminum oxide pattern: deposition and evaluation of its characteristic properties

Suitable coatings on electronic packaging substrates are generally preferred to surround the internal components, protect them from adverse conditions, and improve heat-dissipating performance. Such coatings are developed using different deposition techniques to attain a cosmetic appearance on a single sheet, preferably aluminium alloys. These coatings have to overcome certain challenges, including heat dissipation and mechanical robustness. In this study, a nickel–boron (NiB) binary alloy was sealed and deposited on an already developed nanoporous anodic aluminium oxide (AAO) pattern using an electroless deposition method. The performance is studied with respect to different deposition times. The resulting NiB layer has a nano nodular-like morphology with a 0.95-μm layer thickness. The structural analysis shows a mixture of amorphous and crystalline nature with sharp Ni peaks (111), (220), including the crystallite size of 377 nm. Compared with the bare Al substrate, the 1-hr NiB sealing on AAO has a significant reduction in thermal resistance (Rth) to 29.65%, a rise in junction temperature (Tj) to 27.36%, and improved bulk thermal conductivity (k) to 50.1%. In addition, this binary NiB exhibits a roughness of 0.89 μm, an indentation hardness of 2560 MPa, and a scratch hardness of 8764 MPa. Results show enhanced properties of the AAO sealed binary NiB coating as a feasible option for packaging substrates.

Experimental investigation on effect of accelerated speed and rotor material on life of implantable micro-infusion pump tubing

Peristaltic pumps have been put to use in various biomedical applications like devices for the transfer of body fluids as well as devices for controlled release of medication, including implantable infusion pumps. Out of the various components of a peristaltic pump, tubing is considered the most vulnerable part. This study focuses on the performance of Silicone micro-pump tubing used in such an implantable drug delivery device. Long-term implantable medical devices are expected to be operational for about 10 years. But experimental testing of the reliability of components under normal working speeds are time-consuming and thus delays the product development cycle. While simulating the conditions in the laboratory under accelerated speeds, the effect of increasing the speed must be accounted. In this study, the effect of accelerated speed and rotor material on pump tubing life is investigated. A test jig is developed which simulates the running conditions of the infusion pump for long-duration operation. Different rotor speeds and material configurations are investigated to obtain their effect on long-duration performance. Thermal effects on the roller junctions are studied and found that the Delrin silicone combination has twice the rise in junction temperature than the titanium silicone combination. The failure modes are inspected using microstructure analysis and the best configuration is identified.

Fabrication and thermal transient analysis of Ni-P sealed anodic aluminium oxide for electronic packaging

In recent years, suitable coatings on electronic packaging substrates are focused to improve heat-dissipation from the device hot spot. Nano porous-based anodic aluminum oxide (AAO) was introduced on Al surfaces aiming to improve heat dissipation. In extension, sealing of nano porous AAO using different deposition method is also introduced for thermal management. In this study, nickel–phosphorous (Ni-P) alloy was sealed and deposited on an already developed nanoporous anodic aluminum oxide (AAO) pattern using an electroless deposition method. The AAO is developed on Al5052 alloy using a two-step anodization process and the formation has resulted in 40- to 55-nm pore diameter and 6–7-μm thickness. The performance of Ni-P sealed nanoporous AAO was studied with respect to different deposition times and the characteristics have been studied via field emission scanning electron microscopy, X-ray diffraction, surface roughness profilometry, and thermal transient measurements. The thermal characteristics have been studied via thermal conductivity analyzer and thermal transient measurements. The resulting Ni-P layer has a cauliflower -like morphology with 1.2-μm layer thickness. The structural analysis show a mixture of amorphous and crystalline nature with sharp Ni peaks (111), (200) including the crystallite size as 518 nm. When compared with bare Al substrate, the 2-hr Ni-P sealing on AAO has a significant reduction in total thermal resistance (ΔRth) to 33%, rise in junction temperature (ΔTj) to 29%, and improved bulk thermal conductivity (k) to 41.5%. Results show enhanced properties of Ni-P-sealed AAO composite coating as a feasible option for the electronic packaging substrates.

Reliability Enhancement of Power IGBTs under Short-Circuit Fault Condition Using Short-Circuit Current Limiting-Based Technique

Like the widely-used semiconductor switch, Insulated Gate Bipolar Transistors (IGBTs) are subject to many failures and degradation in power electronic converters. In Short Circuit Fault (SCF), as the most reported failures in IGBTs, drastic, sudden temperature rise, and peak SCF current are widespread failures owing to a relatively long delay of the protection subsystem. This paper proposes a protection strategy to limit the junction temperature rise by limiting the SCF current by adding a small value resistor in the IGBT emitter. Second, it reduces the SCF current to a value much less than the saturated current. With the proposed control approach, sudden temperature rise during SCF is controlled, preventing significant failure in IGBTs. The extension of the permissible SCF time is achieved even for the cases with temporary arcs. A simple control loop activates in the SCF condition and does not create slow transients for the IGBT. The results of this paper are validated through simulation and experiment.

Effect of ambient temperature and heating time on high-power LED

LED is widely used in various fields as a new style of light sources. Today the efficiency of LED electro-optical conversion is only 20%, and the rest of energy release in the form of heat, which is generating higher junction temperature. The junction temperature rise will cause serious thermal problems and affect the performance of the LED. In this paper, we mainly focus on the research of the thermal problem of the high-power LED. The result shows that the junction temperature and thermal resistance of the R and G-based LEDs increase with the increase of the ambient temperature and the heating time. This leads to an increase in operating current, ambient temperature, and usage time during operation of the high-power LED, which causes the low luminous efficiency of the LED, thereby increasing the amount of heat generated, which easily causes aging of the device and permanent light decay. Therefore, reducing the thermal resistance and junction temperature in the previous LED design will greatly help the thermal and optical improvement of the LED.

Comparison between the influence of mechanical vibration and junction temperature rise originated bond wires detachment on the characteristics of IGBT module

As the main device in a power system, the IGBT module works in the frequent power cycle for a long time, resulting to the fluctuation of junction temperature and heavy mechanical stress loading. These two factors threaten the reliability of bond wires and the IGBT module significantly. This study aimed at improving the reliability of the semiconductor device. IGBT dual bridge module was used as the primary research object, establishing the relationship between the bond wires detachment and resistance. MATLAB was used for mathematical analysis to determine the quantitative influence of the two conditions on several static characteristics of the IGBT module. Our study provides more samples and references to monitoring the IGBT bond wires and demonstrates the difference and similarity of these two factors.

Impact of SiC Switch–MOS for Thermal Impedance Evaluation of Power Module

In this paper, thermal impedances of Silicon carbide (SiC) power module assembled with a Schottky Barrier Diode (SBD)–wall–integrated trench MOSFET (SWITCH–MOS) and a conventional trench gate MOSFET (UMOS) are measured. Then they are compared to show the advantage of SWITCH–MOS for thermal impedance measurement. SiC power device is attracting attention as a candidate for future power device, since it can be operated at higher current density and higher switching speed than conventional silicon (Si) power device. The power module packaging technology for SiC power device should have low thermal impedance (both transient and steady state thermal resistance) to bring out a potential ability of the device. Thermal design often has difference from measurement due to various modeling errors such as power device heat generation, module structure, interfacial thermal resistance, and cooling environment. Therefore, accurate thermal impedance measurement is an essential technology. However, the thermal impedance measurement of SiC power modules has the significant issue due to the instability of the body diode built into the SiC–MOSFET. The thermal impedance is the junction temperature rise per heat generation amount of the device. The temperature dependence of the knee voltage of the body diode is used to measure the junction temperature of the MOSFET. Since the knee voltage of SiC–MOSFET changes depending on the gate voltage, a high negative gate bias was necessary to avoid this effect. However, the negative gate bias stress may cause serious device damage such as threshold shift. The SWITCH–MOS which has SBD built in near the MOSFET channel is expected to stabilize the junction temperature measurement and avoid the risk of device deterioration. Figure 1 shows the cross–sectional schematic of the SWITCH–MOS and the conventional UMOS. The SBD are formed on the trench sidewall in SWITCH-MOS, and the device structure is almost same to the UMOS. The temperature is detected by the PiN diode for the UMOS and by the SBD for the SWITCH–MOS. Both of them measure the temperature inside of the MOSFET cell. The appearance of the test module is shown in Fig. 2. Each type of the test module is composed of the SiC die (SWITCH–MOS, UMOS, and SBD), an SiN–AMC insulating circuit substrate and an Al baseplate. The components are attached each other using AuGe solder. The junction temperature is measured from the built–in voltage of the body diode in response to a constant current flowing from the source to the drain. In the case of the UMOS, the gate bias of −18 V is applied. The gate bias is zero for the SWITCH–MOS. The thermal impedance of each test module was measured by static mode (Fig. 3). Then, the thermal structure function was calculated by transient thermal analysis (Fig. 4). Both the thermal impedance and the structure function for the SWITCH–MOS and UMOS were in good agreement. Since the SWITCH–MOS does not need negative gate bias, the threshold shift issue does not occur in principle. In addition, it is possible to perform a transient thermal testing with a large current for a long time. Because the forward degradation does not occur even if a large current is applied to the SBD in the SWITCH–MOS. The SBD built into the SWITCH–MOS makes it easier and more accurate to measure the junction temperature of the SiC–MOSFET. The thermal impedance measurement using SWITCH-MOS not only allows the precise thermal modeling of SiC power modules to be performed, but also has the potential to be applied to the calibration of the thermal design and the evaluation of thermal properties inside of the package structure. Figure 1

Performance of 9.0 W light-emitting diode on various layers of magnesium oxide thin film thermal interface material

MgO thin films were spin coated on aluminum (Al) substrate and used between LED package and heat sink as thin-film heat spreader. Crystallographic studies showed the presence of (111), (200) and (220) orientations related to MgO phases. From the XRD analysis, 10-layers of MgO showed a favorable film thickness (424 nm), crystal size (11.6 nm), microstrain (0.4860 nm) and dislocation density (0.0078 lines/m2). Similarly, low surface roughness (14.6 nm) and depth of peak–valley (71.6 nm) were recorded from 10-layers MgO thin film using Atomic Force Microscopy (AFM) analysis. Relative thermal conductivity of 22.93 W/mK was recorded from the 10-layers MgO film. High value of the difference in total thermal resistance (ΔRth-tot = 3.01 K/W) and rise in junction temperature (ΔTJ = 18.92 °C) were recorded along with good thermal impedance (35 °C) from the 10-layers MgO thin film measured at 700 mA using thermal transient analysis. Overall, MgO thin film coated Al substrates showed an improved performance for the tested LED and, therefore, can be considered as an alternative thermal substrate for LED thermal management.

Power Loss Characterization and Modeling for GaN-Based Hard-Switching Half-Bridges Considering Dynamic on-State Resistance

Gallium nitride enhancement-mode high electron mobility transistors (GaN E-HEMTs) can achieve high frequency and high efficiency due to its excellent switching performance compared with conventional Si transistors. Nevertheless, GaN HEMTs exhibit a more pronounced dynamic ON-state resistance R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS(ON)</sub> than silicon transistors. The variation of R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS(ON)</sub> is caused by both the static R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS(ON)</sub> due to junction temperature rise and the dynamic RDS(ON) due to the electron trapping. Without a careful decoupling analysis, it is difficult to calculate and model the dynamic R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS(ON)</sub> portion. This article introduces a comprehensive approach of dynamic R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS(ON)</sub> evaluation comprising four techniques: 1) a clamping circuit for both the hard-switching (HS) device and synchronous rectification (SR) device; 2) a junction temperature monitoring technique; 3) control of both the pulse test and soak time; and 4) continuous operation of device under test. Based on the dynamic RDS(ON) test results, a new model of the RDS(ON) variation is developed where two coefficients k <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Tj</sub> and k <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dR</sub> are defined to model the contribution of the heating effect and the impact of the trapping effect, respectively. The RDS(ON) model is validated by the comparison between the calculated and measured junction temperatures of a 650-V/30-A GaN-based half-bridge. Furthermore, a detailed loss breakdown analysis is conducted for the GaN-based HS half-bridge. The results show that the switching losses, E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> and E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> , are the dominant loss factors with high switching frequency. At last, the possible efficiency improvements are also discussed in detail.