Junction Logic Research Articles

Radiation Response of Domain-Wall Magnetic Tunnel Junction Logic Devices

Radiation Response of Domain-Wall Magnetic Tunnel Junction Logic Devices

Intrinsically stretchable ionoelastomer junction logic gate synchronously deformable with liquid metal

Liquid-free ionic conductors, known as ionoelastomers, are of great interest because of their potential for developing reliable and resilient ionic devices with elastic mechanical properties. This study presents an intrinsically stretchable diode consisting of a highly stretchable ionoelastomer bilayer vertically stacked with liquid metal electrodes. The bilayer contains two types of ionoelastomer networks: one containing fixed anions with mobile cations and one containing fixed cations with mobile anions. Both ionoelastomers use 2-hydroxyethyl acrylate to provide high stretchability. The junction between the two ionoelastomers creates a diode with excellent non-Faradaic ionic current rectification. The voltage-dependent modulation of the ionic double layer at the interface between the two ionoelastomers provides the rectification. The elastic diode works under cyclic loading to a uniaxial stretch ratio of 6 (strain of 500%), allowing the development of a highly stretchable ionic OR logic gate.

Toward Efficient Logic-in-Memory Computing With Magnetic Reconfigurable Logic Circuits

Logic-in-memory (LIM) structures are promising candidates to obviate limitations of the conventional von Neumann architecture, especially in big data applications, such as image processing. In this paradigm, simple logic operations are embedded in memory to perform basic processes and consequently decrease the workload of the main processor. This letter presents an efficient hybrid fin field-effect transistor and magnetic tunnel junction (MTJ) logic structure compatible with all kinds of memory and which performs <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nor/or</small> and <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nand/and</small> operations. The design utilizes MTJs to obtain different voltage levels and two sense amplifiers to generate the outputs. Simulation results assert that the design improves the delay and power by 33% and 20%, respectively, compared to its state-of-the-art counterparts. Moreover, the magnetic LIM structure is appropriately utilized in image processing applications, such as minimum and maximum image filters, for preparing intermediate data. In the case study, high-level simulations indicate that the design reduces the delay and power by 31% and 21%, respectively.

Design and implementation of reversible logic gates using silicene-based p–n junction logic devices

Advancements in adiabatic quantum computing have enabled a rapid development in thermodynamically reversible logic circuits, which can reduce energy wastage to almost negligible levels. Various reversible logic gates using silicene-based multiplexer logic devices (SMLDs) are designed and demonstrated herein using Verilog-A, then validated by SPICE circuit simulations. The results confirm that the various reversible gates correctly implement the corresponding truth tables, thereby validating the use of SMLDs as building blocks for such gates. The SMLD-based reversible logic gate designs enable a reduction in hardware complexity by 76.92–80.64% compared with complementary metal–oxide–semiconductor (CMOS) technology and a 50% reduction in hardware compared with pass transistor logic-based designs, respectively.

Verilog-A modeling of a silicene-based p–n junction logic device: simulation and applications

One-atom-thick silicene sheets exhibit excellent electronic characteristics that can enable next-generation intelligent and miniaturized integrated circuits. Recent developments in electrostatic doping processes have shown that it is possible to design a multifunction p–n junction-based device that can be used in digital circuits. The Klein tunneling across a silicene p–n junction can convert the simple p–n junction into a gate-controlled Veselago lens. Thus, the transmittance of Dirac fermions can be electrically tuned for high-speed tunneling. In this paper, a large-signal model for a silicene-based multiplexer logic device (SMLD) is designed in Verilog-A and validated through circuit simulations in SPICE. The model is then used to design the basic logic gates. The SMLD-based logic gates outperform those based on conventional technology, showing reductions of hardware complexity and propagation delay by 83% and 91%, respectively.

Performance analysis of differential spin hall effect (DSHE)-MRAM-based logic gates

PurposeThe purpose of this paper is to analyze and compare the characteristics of hybrid conventional complementary metal oxide semiconductor/magnetic tunnel junction (CMOS/MTJ) logic gates based on spin transfer torque (STT) and differential spin Hall effect (DSHE) magnetic random access memory (MRAM).Design/methodology/approachSpintronics technology can be used as an alternative to CMOS technology as it is having comparatively low power dissipation, non-volatility, high density and high endurance. MTJ is the basic spin based device that stores data in form of electron spin instead of charge. Two mechanisms, namely, STT and SHE, are used to switch the magnetization of MTJ.FindingsIt is observed that the power consumption in DSHE based logic gates is 95.6% less than the STT based gates. DSHE-based write circuit consumes only 5.28 fJ energy per bit.Originality/valueThis paper describes how the DSHE-MRAM is more effective for implementing logic circuits in comparison to STT-MRAM.

Design Requirements for a Spintronic MTJ Logic Device for Pipelined Logic Applications

Spintronic devices have been spotlighted due to their nonvolatility and potential for low-voltage operation. However, their potential performance and energy efficiency require greater scrutiny. In this paper, a circuit-level energy-performance analysis is used to derive the design requirements for a spintronic magnetic tunnel junction logic device, mLogic , for pipelined logic applications. An analytical equation for the domain wall mobility of mLogic is derived to predict the performance of future designs and used to point to key directions for further device improvement. We show that the energy dissipation of a logic pipeline under delay constraints is a convex function of the write/read-path resistance ratio and the supply voltage. Scaling the supply voltage can reduce the energy dissipation at the expense of switching speed, but is limited by an extrinsic pinning effect and thermal noise. The energy reduction by maximizing the tunnel magnetoresistance (TMR) will be saturated for TMR larger than 100. But maximizing TMR can mitigate the thermal noise limit of scaling the supply voltage. The energy gap between MOSFETs and mLogic gets smaller for more advanced technology nodes. With 32-nm technology, a future mLogic design can be more optimal than MOSFETs in low-power and low-performance applications, such as emerging Internet-of-Things devices.

Magnetotunneling Junction Logic and Memory: Low-energy logic paradigms for the next decade and beyond

The rapid increase in demand for computational and signal processing prowess calls for radical and revolutionary advances in reliable, energy-efficient, and dense computing architectures. The traditional complementary metal?oxide semiconductor (CMOS) field-effect-transistor-based processors are hardly up to the task because of the excessive energy dissipation that they are burdened with and the fact that CMOS is volatile and thereby inherently incapable of storing data indefinitely.

The universal magnetic tunnel junction logic gates representing 16 binary Boolean logic operations

The novel devices are expected to shift the paradigm of a logic operation by their own nature, replacing the conventional devices. In this study, the nature of our fabricated magnetic tunnel junction (MTJ) that responds to the two external inputs, magnetic field and voltage bias, demonstrated seven basic logic operations. The seven operations were obtained by the electric-field-assisted switching characteristics, where the surface magnetoelectric effect occurs due to a sufficiently thin free layer. The MTJ was transformed as a universal logic gate combined with three supplementary circuits: A multiplexer (MUX), a Wheatstone bridge, and a comparator. With these circuits, the universal logic gates demonstrated 16 binary Boolean logic operations in one logic stage. A possible further approach is parallel computations through a complimentary of MUX and comparator, capable of driving multiple logic gates. A reconfigurable property can also be realized when different logic operations are produced from different level of voltages applying to the same configuration of the logic gate.

Complementary Magnetic Tunnel Junction Logic

This brief proposes and analyzes a novel logic family composed solely of magnetic tunnel junctions (MTJs) to form complimentary pull-up and pull-down networks. This logic family solves the challenge of direct cascading in spintronic logic circuits while also providing non-volatile data storage. The increased logic density possible with complementary MTJs coupled with a charge pulse switching mechanism driven by ferromagnet polarization permits highly efficient logical computation. Furthermore, the presence of non-volatile memory within the logic structure provides a feasible hardware for non-von Neumann computer architectures.

Reliability Analysis and Comparison of Implication and Reprogrammable Logic Gates in Magnetic Tunnel Junction Logic Circuits

Non-volatile logic is a promising solution to overcome the leakage power issue which has become an important obstacle to scaling of CMOS technology. Magnetic tunnel junction (MTJ)-based logic has a great potential, because of the non-volatility, unlimited endurance, CMOS compatibility, and fast switching speed of the MTJ devices. Recently, by direct communication between spin-transfer-torque-operated MTJs, several realizations of intrinsic logic-in-memory circuits have been demonstrated for which the MTJ devices are used simultaneously as memory and computing elements. Here, we present a reliability analysis of the MTJ-based logic operations and show that the reliability is an essential prerequisite of these MTJ-based logic circuits. It is demonstrated that for given MTJ device characteristics, the implication logic architecture, a new kind of logic based on material implication, significantly improves the reliability of the MTJ-based logic as compared to the reprogrammable logic architecture which is based on the conventional Boolean logic operations AND, OR, etc. Implementing the implication gates in spin-transfer torque magnetic random access memory arrays provides pure electrical read/write and logic operations and also allows fan-out to multiple outputs.

Wafer Bumping Process and Inter-Chip Connections for Ultra-High Data Transfer Rates in Multi-Chip Modules With Superconductor Integrated Circuits

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> Josephson junction logic cells and superconductor microstrip lines are able to process and transfer digital data with rates up to several hundred GHz as has been demonstrated in single-chip experiments. However, the existing chip-level bumping technique in InSn solder and resulting inter-chip connections do not allow expanding these rates to multi-chip circuits. We developed a wafer-level bumping technology using lithographically-defined bumps deposited either by e-beam evaporation or electroplating, and proposed and implemented a novel design of high-frequency chip interconnects. Chip-to-chip single-flux-quantum pulse transmission rates reaching 110 GHz have been achieved. The observed rates were limited not by the interconnects but by the speed of on-chip test circuitry fabricated in the framework of 4.5 <formula formulatype="inline"> <tex Notation="TeX">${\rm kA/cm}^{2}$</tex></formula> HYPRES process for superconductor integrated circuits. Experimental results on adhesive-bonded and reflow-bonded multi-chip modules (MCMs) with Au and InSn bumps are presented, and effective parameters of the new interconnect design and MCM technology are discussed. </para>

A new approach for analysis of on-chip interconnections in integrated Josephson junction logic schemes

Currently, clock speeds of up to 100 GHz of the superconducting digital circuitson the base of the propagation of single flux quanta are under consideration.In order to make full use of the high operation speed,limitations due to the interconnections are investigated using a new analysismethod. The modelling is described and a comparison to a conventional approach is made.The results provide conditions of practical use for the interconnect design on chip-level.

Analysis of electromagnetic coupling effects in integrated Josephson junction logic devices by the FDTD technique

A very important step of the design of circuits and devices in the Josephson junction technology is the complete and correct calculation of their electrical characteristics. Due to the very high clock speed of up to 100 GHz, dynamic effects like the electromagnetic coupling start to play a significant role over the operation of the system. The presented work reports on the implementation of the FDTD technique for the description of the electromagnetic coupling effects in the Josephson devices. Some typical microstrip layouts are considered strictly taking in account the technological specifications. The obtained results are analyzed in respect to the constraints, which the coupling effects impose on the lateral dimensions of the microstrip lines.

Future heat transfer concerns in Josephson junction computers

Using the superconducting properties of Josephson junctions enable extremely high switching speeds unmatched in semiconducting electronics. Much research has been conducted in recent decades in order to produce high performance electronics based on Josephson junction logic. In addition to the high speeds attainable by this technology, also of significance is the very low heat dissipated by Josephson circuits. Josephson devices have made great strides in the last ten years with microprocessors reaching levels of integration as high as 10/sup 5/ junctions/cm/sup 2/. Dissipation in these devices is easily managed, but integrations reaching 10/sup 7/ must be considered if Josephson electronics are to compete with the complexity and functionality of semiconducting electronics. Coupling this level of integration with dissipations of 0.34 and 2.98 /spl mu/W/junction in low and high temperature cases respectively, produces large heat fluxes difficult to remove at cryogenic temperatures. While other technical difficulties currently overshadow heat transfer concerns, the future of Josephson electronics research will likely need to address them.

Complementary Josephson junction devices and circuits: a possible new approach to superconducting electronics

We present a superconducting logic family whose operation relies on the availability of a current gain greater than one, based on the analogy to semiconductor complementary metal-oxide-semiconductor (CMOS) logic family. The Complementary Josephson Junction (CJJ) logic family utilizes two types of nonlatching devices: a conventional device and a complementary device. The conventional device has a finite critical current, and the complementary device has zero critical current with no input applied. When the input is high, the complementary device has a finite critical current, while the conventional device has zero critical current. The bias current can be steered between a branch with a complementary device and a branch with a conventional device performing logic (and memory) functions. We can also use a resistor as a load to a complementary device. We call this circuit topology the Resistor Complementary Josephson Junction (RCJJ) family. It is analogous to the semiconductor PMOS/resistor logic family. In this paper, we investigate methods of realizing complementary devices, and we present a preliminary analysis of speed, margins, and power dissipation in simple CJJ and RCJJ inverter circuits.

Optimization of hybrid JJ/CMOS memory operating temperatures

A major drawback of present superconducting electronics is the lack of suitable large scale memory. One approach to circumvent this problem is to use semiconducting CMOS memory in conjunction with the fast Josephson junction (JJ) logic. This requires operating the CMOS memory at cryogenic temperatures. The speed of CMOS circuits has been shown to increase at cryogenic temperatures. Further increase in speed can be obtained by using JJ sense circuits in the CMOS memory. Preliminary results show that access time of 1.5 ns should be possible with this hybrid JJ/CMOS approach using 1.2 micron CMOS, and JJ sense and interface circuits. We also report the results of an analysis of the optimal operating temperature of such hybrid memories in conjunction with refrigeration requirements in light of the emerging cryocooler technologies.

Superconductive crossbar system for communication applications

This paper reviews current efforts toward the integration of a high-speed crossbar switch for digital communication applications. This system is an intelligent switching matrix for 128 inputs and 128 outputs, each capable of 2 Gbs (10 9 bits per second). An array of Josephson junction integrated circuits are interconnected with the use of a superconductive multichip module maintained at 4.2 K. This module is connected to room-temperature electronics by means of flexible cables, each containing impedance-matched microstrip transmission lines. Room-temperature interface electronics will permit interconversion between standard level input/output signals and Josephson junction logic levels.

Josephson compensating junction logic

A Josephson superconducting quantum interference device (SQUID) digital logic family was developed that uses the R/sub nn/ region of a Josephson junction (JJ) to compensate for variations in where R/sub nn/ is the effective resistance of a JJ in the linear I-V region beyond the gap. The basic compensating junction logic (CJL) circuit is two 2-input-OR 1-2-1 interferometer isolators that, when switched, inject current into a 2-input-AND 1-2-1 interferometer. The R/sub nn/ region of several JJs is used in series with a resistor to set the current from the power supply to the 2-input-OR interferometers. The 2-input-AND interferometer is implemented with both current injection and magnetic coupling. The latch circuit uses both current injection and magnetic coupling design techniques to increase the range of I/sub O/, inductance, and resistance variation over which the latch will function correctly. Experimental measurements of CJL circuits are described.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

An integration of all refractory Josephson logic LSI circuit

An integration process for the fabrication of an all refractory Josephson LSI logic circuit is described. In this process, niobium nitride and niobium double-layered Josephson junctions were integrated using a reactive ion etching with a 2.5 μm minimum feature. A highly selective and anisotropic RIE process and a planarizing technology have been developed for intagrating a circuit with LSI complexity. For evaluating the process capability, test vehicle circuits with MSI/LSI level complexity have been designed and fabricated using this process. An 8 bit ripple carry adder and a 4×4 bit parallel multiplier have been integrated with Josephson four junction logic ( 4JL ) gates, the largest of which contains more than 2800 Josephson junctions. Both functionality and high-speed performance testings have been successfully performed with these test circuits.