Optimization of hybrid JJ/CMOS memory operating temperatures

Abstract

A major drawback of present superconducting electronics is the lack of suitable large scale memory. One approach to circumvent this problem is to use semiconducting CMOS memory in conjunction with the fast Josephson junction (JJ) logic. This requires operating the CMOS memory at cryogenic temperatures. The speed of CMOS circuits has been shown to increase at cryogenic temperatures. Further increase in speed can be obtained by using JJ sense circuits in the CMOS memory. Preliminary results show that access time of 1.5 ns should be possible with this hybrid JJ/CMOS approach using 1.2 micron CMOS, and JJ sense and interface circuits. We also report the results of an analysis of the optimal operating temperature of such hybrid memories in conjunction with refrigeration requirements in light of the emerging cryocooler technologies.