Abstract
Currently, clock speeds of up to 100 GHz of the superconducting digital circuitson the base of the propagation of single flux quanta are under consideration.In order to make full use of the high operation speed,limitations due to the interconnections are investigated using a new analysismethod. The modelling is described and a comparison to a conventional approach is made.The results provide conditions of practical use for the interconnect design on chip-level.
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