Verilog-A modeling of a silicene-based p–n junction logic device: simulation and applications

Abstract

One-atom-thick silicene sheets exhibit excellent electronic characteristics that can enable next-generation intelligent and miniaturized integrated circuits. Recent developments in electrostatic doping processes have shown that it is possible to design a multifunction p–n junction-based device that can be used in digital circuits. The Klein tunneling across a silicene p–n junction can convert the simple p–n junction into a gate-controlled Veselago lens. Thus, the transmittance of Dirac fermions can be electrically tuned for high-speed tunneling. In this paper, a large-signal model for a silicene-based multiplexer logic device (SMLD) is designed in Verilog-A and validated through circuit simulations in SPICE. The model is then used to design the basic logic gates. The SMLD-based logic gates outperform those based on conventional technology, showing reductions of hardware complexity and propagation delay by 83% and 91%, respectively.