Design Requirements for a Spintronic MTJ Logic Device for Pipelined Logic Applications

Abstract

Spintronic devices have been spotlighted due to their nonvolatility and potential for low-voltage operation. However, their potential performance and energy efficiency require greater scrutiny. In this paper, a circuit-level energy-performance analysis is used to derive the design requirements for a spintronic magnetic tunnel junction logic device, mLogic , for pipelined logic applications. An analytical equation for the domain wall mobility of mLogic is derived to predict the performance of future designs and used to point to key directions for further device improvement. We show that the energy dissipation of a logic pipeline under delay constraints is a convex function of the write/read-path resistance ratio and the supply voltage. Scaling the supply voltage can reduce the energy dissipation at the expense of switching speed, but is limited by an extrinsic pinning effect and thermal noise. The energy reduction by maximizing the tunnel magnetoresistance (TMR) will be saturated for TMR larger than 100. But maximizing TMR can mitigate the thermal noise limit of scaling the supply voltage. The energy gap between MOSFETs and mLogic gets smaller for more advanced technology nodes. With 32-nm technology, a future mLogic design can be more optimal than MOSFETs in low-power and low-performance applications, such as emerging Internet-of-Things devices.