Polymorphic Hybrid CMOS-MTJ Logic Gates for Hardware Security Applications

Abstract

Various hardware security concerns, such as hardware Trojans and IP piracy, have sparked studies in the security field employing alternatives to CMOS chips. Spintronic devices are among the most-promising alternatives to CMOS devices for applications that need low power consumption, non-volatility, and ease of integration with silicon substrates. This article looked at how hardware can be made more secure by utilizing the special features of spintronics devices. Spintronic-based devices can be used to build polymorphic gates (PGs), which conceal the functionality of the circuits during fabrication. Since spintronic devices such as magnetic tunnel junctions (MTJs) offer non-volatile properties, the state of these devices can be written only once after fabrication for correct functionality. Symmetric circuits using two-terminal MTJs and three-terminal MTJs were designed, analyzed, and compared in this article. The simulation results demonstrated how a single control signal can alter the functionality of the circuit, and the adversary would find it challenging to reverse-engineer the design due to the similarity of the logic blocks’ internal structures. The use of spintronic PGs in IC watermarking and fingerprinting was also explored in this article. The TSMC 65nm MOS technology was used in the Cadence Spectre simulator for all simulations in this work. For the comparison between the structures based on different MTJs, the physical dimension of the MTJs were kept precisely the same.