Junction Field Effect Transistor Research Articles

GaN Vertical-Channel Junction Field-Effect Transistors With Regrown p-GaN by MOCVD

We report an experimental demonstration of GaN-based vertical-channel junction field-effect transistors (VC-JFETs). A p-GaN regrowth by metalorganic chemical vapor deposition (MOCVD) and a subsequent self-planarization process were developed to fabricate the GaN VC-JFETs. Fin-like channel regions were patterned by electron beam lithography (EBL) and aligned to ${m}$ -plane or ${a}$ -plane. The electrical properties of lateral and vertical p-n junctions were characterized to verify the effectiveness of the p-GaN regrowth. Both VC-JFETs with ${m}$ -plane and ${a}$ -plane channels show decent gate modulation. We further discussed important factors that may affect the device performance including interfacial impurities and nonuniform acceptor distribution. This work highlights the successful demonstration of GaN VC-JFETs and lateral p-n junctions by an etch-then-regrow process, providing valuable information and reference for the further development of GaN power electronics.

Technological and devices modeling of complementary JFETs over a wide temperature range

The article presents the results of process and device modeling results of complementary junction field-effect transistors (JFET). The models necessary for calculating the JFET in the temperature range down to cryogenic were described: the Klaassen model of the carriers mobility (Phillips company model) and Shockley-Read-Hall recombination model, taking into account the doping dependence, Lackner's model of avalanche multiplication, Fermi-Dirac statistics, Slotboom model, designed to describe the dependence of the band gap on the doping concentration. These models take into account the effect of temperature. We have described in detail the model of incomplete ionization of an impurity, which determines the concentration of charge carriers at cryogenic temperatures. The TCAD-based JFET self-heating effect is simulated using a simplified model that significantly reduces the calculation time compared to the thermodynamic model. Studies on the selection of an algorithm for calculating a system of differential equations in the temperature region are carried out. It is shown that the SLIP90 algorithm provides calculations in the entire temperature range down to T = 25 K. The article shows that modification of the design can significantly affect the choice of calculation algorithm. The dependences of the main JFET parameters are analyzed taking into account the selected models on temperature and constructive and technological solutions are proposed to reduce the influence of ultra-low temperatures on the parameters of complementary JFETs.The research results showed that reducing the cut-off voltage reduces the influence of temperature on the shorted-gate drain current JFET in the temperature range. At the same time, n-channel transistors have advantages in terms of a smaller change in parameters over the temperature range down to the temperatures at which the “freezing out” of the impurity charge carriers begins. Several types of transistor topologies were simulated in the temperature range, which showed that the value of the shorted-gate drain current increases linearly with the number of gates. However, there are differences in the dependence of the main parameters in the temperature range depending on the design of the layers of complementary JFETs. Using the emitter region as the top gate weakly affects the parameters of the n-channel JFET in the case of the formation of complementary JFETs in the microwave complementary bipolar technological process, and for the p-channel JFET the temperature stability of the parameters deteriorates. For the p-channel transistor with a gate based on the base region, the temperature stability over the range ΔT = 150–330 K of the shorted-gate drain current is higher than for the transistor with a gate based on the emitter. For the n-channel transistor, the dependence is inverse. Over the range ΔT = 150–77 K, the dependence of the parameters of the transistors for two structures does not differ. In principle, the results show that the change in the ambient temperature has a greater effect on the p-channel transistor than on the n-channel.

Nonvolatile Associative Memory Design Based on Spintronic Synapses and CNTFET Neurons

Many advances have been made in developing bio-inspired intelligent systems for performing important tasks like pattern association, which cannot be performed effectively by the conventional computer architectures. This paper presents a novel nonvolatile associative memory based on spintronic synapses utilizing magnetic tunnel junction (MTJ) and carbon nanotube field-effect transistors (CNTFET)-based neurons. MTJs introduce fascinating features like reconfigurability, nonvolatility, and high endurance to the design, while CNTFETs compensate for the flaws of the conventional transistors in deep nanoscale nodes. The comprehensive simulations validate the functionality of the proposed synaptic cell, and neuron, even in the presence of major process variations. The application of the proposed synaptic cell and neuron in the hardware realization of multi-associative memories is also investigated. The simulation results indicate that the proposed hardware-based multi-associative memory performs similar to its ideal software-based counterpart with a less than 3 percent difference in the successful recall rate. It also noteworthy that since the input and output of the proposed design are logical ‘0’ and ‘1’, the proposed design does not need any extra component for voltage conversion.

Design of Ion-Implanted Junction Termination Extension for Vertical GaN Pin Rectifiers

Gallium-nitride and related materials have become suitable semiconductor platforms for next-generation power electronic devices. This materials system leverages unique properties of wider energy bandgap, higher carrier mobility, and ultrashort carrier recombination lifetime to achieve much improved bipolar switching characteristics when compared to Si- or SiC-based counterparts. In recent years, vertical GaN switches such as PIN rectifiers, junction barrier Schottky (JBS) diodes, and junction field-effect transistors (JFETs) have been actively sought in hopes to achieve low-loss device performance at kilo-volt (kV) operation range. Over the years, significant progresses in low-defect-density substrate preparation and high-quality epitaxial growth using metalorganic chemical vapor deposition (MOCVD) reactors, along with robust fabrication processing techniques helped achieve many impressive GaN-based power device demonstrations. As vertical GaN devices operate at the kV ranges, proper engineering of the electric field is a key to exploiting the ultimate device performance. To this end, several device-level design strategies such as field plates, beveled sidewalls, and junction termination extensions have been studied. In the context of realizing a planar device topology in GaN materials systems, ion implantation into GaN materials systems offer new opportunities to provide precise control of inhomogeneous carrier distribution for the creation of versatile doping profiles and geometries such as selectively doped regions or highly resistive regions at arbitrary locations in GaN devices.In this presentation, we will discuss a study of the floating guard rings (FGRs) designs that utilize a nitrogen-ion implantation isolation technique. The designs can effectively mitigate the electric field crowding effect and enable robust avalanching capability in vertical GaN PIN rectifiers. Using 1.2-kV GaN PIN rectifiers as design examples, a set of numerical simulation study was performed using a TCAD-Sentaurus software package. The results showed that a closely packed FGRs with a gap of adjacent FGRs in the range of 1-3 microns, a width of the FGRs in the range of 4 to 6 microns, along with a variable-width FGR design toward the outer rings can effectively suppress the peak electric field distribution at edge of the main junction and the surface of junction termination extensions. For example, consider a GaN PIN rectifier structure with a drift layer that consists of 6 microns of unintentionally doped (UID) GaN (n= 5×1015 cm-3) and a 4-micron-thick lightly doped GaN (n = 2×1016 cm-3). The FGR structures can be formed by creating highly resistive GaN regions in the epitaxially grown p-GaN layer using an ion implantation technique. In this design, five of the FGRs have 1-micron-wide undoped GaN and a 6-micron-wide p-GaN region in the p-GaN layer. The outermost FGR (the 6th FGR) is designed to have a 2-micron-wide undoped GaN and 5-micron-wide p-GaN extension. The resulting field distribution showed an effective suppression of the field crowding effect at the edge of the main junction (Figure 1(a)) and a smooth electric potential drop along the lateral direction can be achieved (Figure 1(b)). As shown in Figure 2, the electric field distribution at the vertical junction was plotted for two FGR designs with and without a metal plate on top of the p-GaN region. The electric field distribution of the main junction was also plotted for comparison. It is clearly shown that the peak electric field at the vertical junction is effectively reduced with the metal-plated FGRs by >10% when compared to a non-plated FGRs. Reduced peak electric field in typically high-electric-field regions can safeguard the device from experiencing premature breakdown for robust switching operations. We found that 6 FGRs with a total lateral extension of <45 microns from the main pn junction are sufficient to provide effective junction termination for 1.2 kV devices. Such designs could also support for devices with a blocking voltage up to 1.6 kV.FGR designs were implemented in GaN PIN rectifiers for experimental validation. The fabrication processing of vertical GaN PIN rectifiers was grown on n-type free-standing or bulk GaN substrates using a MOCVD reactor. The cathode was formed by depositing Ti/Al-based ohmic contact on the backside of the wafer, and the anode electrode was formed on the topside p-type GaN layer. Nitrogen-ion implantation was employed to create FGR structures and served as a mean of inter-device isolation. Detailed design strategies of the FGRs, device processing and device characterizations will be discussed in the conference. Figure 1

All‐Oxide Transparent Thin‐Film Transistors Based on Amorphous Zinc Tin Oxide Fabricated at Room Temperature: Approaching the Thermodynamic Limit of the Subthreshold Swing

AbstractThin‐film transistors (TFTs) based on transparent amorphous oxide semiconductors (TAOSs) have become essential building blocks for a broad range of electronics, since TAOSs facilitate large‐scale fabrication at moderate temperatures and hence feature compatibility with flexible substrates. An emerging indium‐free alternative to the widely commercially exploited indium gallium zinc oxide (IGZO) is amorphous zinc tin oxide (ZTO); however, according to previous reports, achieving acceptable performance of ZTO‐based devices fabricated at temperatures below 300 °C is still challenging to date. Here, key properties of the first all‐oxide and fully transparent metal‐semiconductor field‐effect transistors (MESFETs), metal‐insulator‐semiconductor field‐effect transistors (MISFETs) and junction field‐effect transistors (JFETs) based on amorphous ZTO are compared, employing PtOx, HfOy, and p‐type NiO as gate, respectively. All individual layers have been deposited exclusively at room temperature and do not require any additional postdeposition annealing to obtain sufficient device functionality. Demonstrated TFTs exhibit reasonable current on/off ratios of over six orders of magnitude with subthreshold swings as low as 61 mV dec–1 at room temperature. Transistor characteristics have been recorded for several weeks to study performance consistency over time and are further investigated regarding their stability under bias stress.

Novel Self-Modulated Lateral Superjunction Device Suppressing the Inherent 3-D JFET Effect

A novel self-modulated superjunction lateral double-diffused MOSFET (SM-SJ LDMOS) is proposed and experimentally realized in this letter. When a SJ is introduced into a lightly doped N-drift region, the 3-D depletion regions appear surrounding the P-pillars. This 3-D junction field effect transistor (JFET) effect decreases the current paths in both N-pillars and N-drift, causing a largely increased specific on-resistance ${R} _{\text {on,sp}}$ especially for the SJ with a narrow cell pitch. To suppress the inherent 3-D JFET effect, the SM-SJ structure is proposed by replacing the P-pillars with a series of P-islands. These P-islands with linearly reduced lengths modulate the surface electric field to increase the breakdown voltage ${V} _{{\text {B}}}$ while the N-drift areas between P-islands weaken the 3-D JFET effect to reduce ${R} _{\text {on,sp}}$ . Compared with the conventional SJ device, the measured ${V} _{\text {B}}$ of the SM-SJ LDMOS is increased by 53.1% from 260 V to 398 V with ${R} _{on,sp}$ reduced by 22.3% from 35.4 $\text{m}\Omega ~\cdot $ cm2 to 27.5 $\text{m}\Omega ~\cdot $ cm2.

A Normally-off Copackaged SiC-JFET/GaN-HEMT Cascode Device for High-Voltage and High-Frequency Applications

A 1200-V/100-mΩ silicon carbide (SiC) junction field-effect-transistor (JFET)/ gallium nitride (GaN) high-electron-mobility-transistor (HEMT) hybrid power switch is demonstrated, which features a flip-chip copackaged cascode configuration incorporating a vertical SiC JFET and a lateral GaN-HEMT. The high-voltage SiC-JFET provides the high-voltage blocking capability while the low-voltage GaN-HEMT enables the normally- off gate control with superior switching characteristics. Compared to conventional SiC-JFET/Si- mosfet cascode devices, the SiC-JFET/GaN-HEMT cascode device exhibits fast switching speed, which has been validated by systematic characterizations including static/dynamic device-level measurements and board-level hard-switching tests. Meanwhile, the device is free from several notorious issues of high-voltage GaN power transistors such as dynamic on -state resistance degradation and threshold voltage shift. Such a wide-bandgap semiconductor-based hybrid switch is suitable to be deployed in high-power and high-efficiency power conversion systems.

Experimental Study on Short-Channel Effects in Double-Gate Silicon Carbide JFETs

Short-channel effects (SCEs) in double-gate silicon carbide junction field-effect transistors (JFETs) fully fabricated by ion implantation are experimentally investigated. The threshold voltage shift, drain-induced barrier lowering, and subthreshold slope degradation are clearly observed in the fabricated p- and n-JFETs. The SCEs are quantitatively evaluated by comparing with the theoretical values obtained by solving a 2-D Poisson equation, which shows good agreement with experiments. The dominant parameter for the SCEs in JFETs is the ratio of the channel length ( ${L}$ ) to the channel thickness ( ${a}$ ), and the device scaling rule to avoid the SCEs is estimated to be ${L}/{a} > {3}$ .

Dv/Dt-Control of 1200-V Normally-off SiC-JFET/GaN-HEMT Cascode Device

A normally- off SiC-JFET/GaN-HEMT cascode device is recently proposed, featuring a cascode configuration that incorporates a high-voltage (i.e., 1200 V) SiC junction field effect transistor (JFET) and a low-voltage GaN high electron mobility transistor (HEMT). This cascode device exhibits superior thermal stability and switching performance compared to the SiC MOSFETs, but also inevitably presents challenge in dv/dt -control as the input gate does not directly control the high-voltage JFET. Since dv/dt -control is of great importance to the management and suppression of electromagnetic interference in power electronics systems, methods of controlling the dv/dt rates of SiC/GaN cascode devices need to be developed. In this article, we conduct systematic investigation on different dv/dt control schemes with theoretical analysis and experimental evaluation. A dv/dt -control method based on diode-clamped external JFET gate resistor is proposed and evaluated by comparing it with other more conventional methods. The proposed dv/dt -control method is verified to provide a balanced dv/dt -control on the device turn- on and turn- off .

High-mobility junction field-effect transistor via graphene/MoS2 heterointerface

Monolayer molybdenum disulfide (MoS2) possesses a desirable direct bandgap with moderate carrier mobility, whereas graphene (Gr) exhibits a zero bandgap and excellent carrier mobility. Numerous approaches have been suggested for concomitantly realizing high on/off current ratio and high carrier mobility in field-effect transistors, but little is known to date about the effect of two-dimensional layered materials. Herein, we propose a Gr/MoS2 heterojunction platform, i.e., junction field-effect transistor (JFET), that enhances the carrier mobility by a factor of ~ 10 (~ 100 cm2 V−1 s−1) compared to that of monolayer MoS2, while retaining a high on/off current ratio of ~ 108 at room temperature. The Fermi level of Gr can be tuned by the wide back-gate bias (VBG) to modulate the effective Schottky barrier height (SBH) at the Gr/MoS2 heterointerface from 528 meV (n-MoS2/p-Gr) to 116 meV (n-MoS2/n-Gr), consequently enhancing the carrier mobility. The double humps in the transconductance derivative profile clearly reveal the carrier transport mechanism of Gr/MoS2, where the barrier height is controlled by electrostatic doping.

Low-Noise Programmable Voltage Source

This paper presents the design and testing of a low-noise programmable voltage source. Such a piece of instrumentation is often required as part of the measurement setup needed to test electronic devices without introducing noise from the power supply (such as photodetectors, resistors or transistors). Although its construction is based on known configurations, here the discussion is focused on the characterization and the minimization of the output noise, especially at very low frequencies. The design relies on a digital-to-analog converter, proper lowpass filters, and a low-noise Junction Field-Effect Transistors (JFET) based voltage follower. Because of the very low level of output noise, in some cases we had to resort to cross-correlation in order to reduce the background noise of the amplifiers used for the characterization of the programmable source. Indeed, when two paralleled IF9030 JFETs are used in the voltage follower, the output noise can be as low as 3 nV/√Hz, 0.6 nV/√Hz and 0.4 nV/√Hz at 1 Hz, 10 Hz and 100 Hz, respectively. The output voltage drift was also characterized and a stability of ±25 µV over 3 h was obtained. In order to better appreciate the performance of the low-noise voltage source that we have designed, its noise performances were compared with those of a set-up based on one of the best low-noise solid-state voltage regulators available on the market. Actual measurements of the current noise in a type-II superlattice photodetector are reported in which the programmable source was used to provide the voltage bias to the device.

High-performance junction field-effect transistor based on black phosphorus/β-Ga2O3 heterostructure

Black phosphorous (BP), an excellent two-dimensional (2D) monoelemental layered p-type semiconductor material with high carrier mobility and thickness-dependent tunable direct bandgap structure, has been widely applied in various devices. As the essential building blocks for modern electronic and optoelectronic devices, high quality PN junctions based on semiconductors have attracted widespread attention. Herein, we report a junction field-effect transistor (JFET) by integrating narrow-gap p-type BP and ultra-wide gap n-type β-Ga2O3 nanoflakes for the first time. BP and β-Ga2O3 form a vertical van der Waals (vdW) heterostructure by mechanically exfoliated method. The BP/β-Ga2O3 vdW heterostructure exhibits remarkable PN diode rectifying characteristics with a high rectifying ratio about 107 and a low reverse current around pA. More interestingly, by using the BP as the gate and β-Ga2O3 as the channel, the BP/β-Ga2O3 JFET devices demonstrate excellent n-channel JFET characteristics with the on/off ratio as high as 107, gate leakage current around as low as pA, maximum transconductance (gm) up to 25.3 µS and saturation drain current (IDSS) of 16.5 µA/µm. Moreover, it has a pinch-off voltage of –20 V and a minimum subthreshold swing of 260 mV/dec. These excellent n-channel JFET characteristics will expand the application of BP in future nanoelectronic devices.

Experimental Study on Mitigation of Lifetime-Limiting Dielectric Cracking in Extreme Temperature 4H-SiC JFET Integrated Circuits

While NASA Glenn Research Center’s “Generation 10” 4H-SiC Junction Field Effect Transistor (JFET) integrated circuits (ICs) have uniquely demonstrated 500 °C electrical operation for durations of over a year, this experimental work has also revealed that physical cracking of chip dielectric passivation layers ultimately limits extreme-environment operating lifetime [1-3]. The prevention of such dielectric passivation cracks should therefore improve IC high temperature durability and yield, leading to more beneficial technology adoption into aerospace, automotive, and energy systems. This report describes Generation 10.2, 11.1, and 11.2 die tested under unbiased and unpackaged accelerated age testing at 500 °C, 600 °C, 720 °C, and 800 °C in air-atmosphere ovens for 100-and 200-hour duration. Additional samples were separately subjected to 10 thermal cycles between the same high temperatures (with 10-hour high-temperature soak each cycle) and 50 °C. It is shown that having two stoichiometric Si3N4 layers in the interconnect dielectric stack substantially decreases the amount of dielectric cracking observed following these oven tests.

20 kV-Class Ultra-High Voltage 4H-SiC n-IE-IGBTs

We demonstrate 20 kV-class 4H-SiC n-channel implantation and epitaxial (IE)-IGBTs having both low on-state voltage and high blocking characteristics. We fabricated n-IE-IGBTs on a (0001) silicon face with free-standing epitaxial layers. Effective carrier lifetime increased significantly from 0.9 μs to 9.6 μs by a lifetime enhancement process. We used the IE structure to suppress an increase of the surface p+-well concentration, reduce implantation damage at the p+-well, and reduce junction field effect transistor (JFET) region resistance by ion implantation as a counter doping. The n-IE-IGBT at 100 A/cm2 on-state voltage and specific differential on-resistance was 8.2 V and 36.9 mΩcm2, respectively, at room temperature with a 30 V gate voltage. The blocking voltage was 26.8 kV at 45.7 μA.

Radiation Hardness of 4H-SiC JFETs in MGy Dose Ranges

Silicon carbide junction field effect transistors (SiC JFETs) were irradiated with gamma-rays up to 9 MGy (H2O). With increasing dose, apparent shift of drain current-gate voltage (ID-VG) curves to negative voltage side as observed for SiC metal oxide semiconductor (MOS) FETs did not take place. No significant difference is observed between drain and gate leakage currents of irradiated JFETs. This strongly indicates that defects as leakage paths were introduced into not bulk region but the interface between bulk and the passivation layer of SiO2. While, the transfer characteristics including threshold voltage and transconductance were slightly changed compared with the pristine sample. After drain voltage (VD) was abruptly applied to 6 V, ID at VG= 0 V increased slowly as a function of time. This indicates that variation of transfer characteristics is attributed to capture and emission process at defects generated in channel region.

Performance test for a pixelated silicon sensor with junction field effect transistor

We fabricated a pixelated silicon sensor with a junction field effect transistor (JFET) on a 650μm thick, high-resistivity (> 5 kΩ⋅cm) n-type double-sided polished 6-in. silicon wafer using a double-sided fabrication process. The JFET, which had a cylindrical structure, acted as a switch to read out charges accumulated in the pixelated sensor. We investigated the electrical characteristics of the pixelated sensor, which had a size of 100μm×100μm. We also measured the drain current as a function of the drain voltage for different gate voltages to examine the switching performance of the JFET and optimized the design parameters of the pixelated sensor for the proper functioning of the switch. Furthermore, the pixelated sensor’s responses under illumination by a light-emitting diode and X-rays were measured. The electrical characteristics and responses of the pixelated sensors are presented in this paper.

InGaZnO Tunnel and Junction Transistors Based on Vertically Stacked Black Phosphorus/InGaZnO Heterojunctions

AbstractThe rapid development of mobile and internet‐of‐thing devices demands continuous scaling of metal–insulator–semiconductor field‐effect transistors for high‐resolution and low‐power displays. However, such technology is limited by inadequate scaling of supply voltage and sophisticated dielectric engineering. Here, to enable continued scaling, indium–gallium–zinc‐oxide (InGaZnO) tunnel field‐effect transistor (TFET) and junction field‐effect transistor (JFET) are designed and fabricated based on vertically stacked black phosphorus (BP)/InGaZnO van der Waals heterojunctions. By varying BP thickness, BP/InGaZnO heterojunctions can be operated as forward rectifying diode, Zener diode, and backward rectifying diode, respectively. Room‐temperature negative‐differential‐resistance behavior with large peak‐to‐valley ratio of 2.1 and high tunneling current density of 160 mA mm−2 is obtained in thick‐BP/InGaZnO heterojunction. On this basis, sub‐thermionic subthreshold swing (SS) of 11 mV dec−1 is achieved in InGaZnO TFET. Meanwhile, the InGaZnO JFET based on thin‐BP/InGaZnO heterostructure exhibits good transistor performance of on/off ratio exceeding 105, high field‐effect mobility of 23.5 cm2 V s−1, negligible hysteresis, and improved SS of 83 mV dec−1. The BP/InGaZnO heterojunction is possibly the only device architecture so far to realize the amorphous metal‐oxide‐semiconductors TFET and JFET, thus providing promising pathways for further thin‐film transistor technology.

A novel 4H-SiC MOSFET for low switching loss and high-reliability applications

A novel 1200 V 4H-SiC MOSFET, which features a current spreading layer, a split-gate and a central P+ implant in the junction field effect transistor region (CSI-MOSFET), is proposed. The CSI-MOSFET achieves a better trade-off among specific on-resistance, maximum electric field in gate oxide and switching loss. The CSI-MOSFET is comprehensively optimized with numerical simulation, and then two kinds of CSI-MOSFETs (FCSI-MOSFET and GCSI-MOSFET with a floating/grounded central P+ implant) are further investigated. Compared with the conventional double implanted MOSFET (VDMOSFET), both FCSI-MOSFET and GCSI-MOSFET demonstrate a smaller on-resistance, and a smaller gate charge. Moreover, a maximum electric field in the gate oxide of 0.92 MV cm−1 is realized in GCSI-MOSFET, without breakdown voltage degradation. To our best knowledge, it is the lowest electric field among those reported on 1200 V SiC MOSFETs. For dynamic characteristics, the FCSI-MOSFET has the largest switching loss and the largest on-state voltage drop, due to the negative charges stored in the floating P+ implant region. On the contrary, the GCSI-MOSFET achieves the same low switching loss as that of the split-gate MOSFET with an extreme short gate length (0.2 μm), because there is no charge in the grounded P+ implant region. Therefore, the GCSI-MOSFET is far superior for low switching loss and high-reliability applications.

Comparison of Fast and Reliable Zero-Voltage Detection Topologies

In this article, three different topologies for a zero-voltage detection (ZVD) are introduced and compared. The ZVD is used to detect a zero-voltage condition (ZVC) across a medium-voltage (MV) switch. This switch can either consist of a single semiconductor device or several devices connected in series. Therefore, the ZVD must be able to withstand the same MV as the switch and at the same time be able to measure a low voltage (LV) across the switch with high reliability and accuracy. First, an emitter follower with an MV metal-oxide semiconductor field-effect transistor ( mosfet ) is introduced as the most trivial ZVD. Second, a current source with silicon carbide (SiC) Schottky barrier diodes to block the MV is introduced. Finally, an emitter-follower cascode using a silicon (Si) SiC super cascode of an LV mosfet and several junction field-effect transistors connected in series to block the MV is introduced. The second and third typologies can be scaled easily to any desired blocking voltage. For each topology prototype, test results are discussed. Their advantages and the corresponding measurement results as well as the application of the different topologies in a 5-MW dual-active bridge converter conclude this work.

(Ultra)Wide-Bandgap Vertical Power FinFETs

FinFET is the backbone device technology for CMOS electronics at deeply scaled technology nodes per Moore's law. Recently, the FinFET concept has been leveraged to develop a new generation of vertical power transistors based on wide-bandgap (WBG) and ultrawide-bandgap (UWBG) semiconductors for kilovolts and high-power applications. The sidewall gate-stack in a vertical power FinFET can rely on either a metal-oxide-semiconductor (MOS) structure or a p-n junction, rendering a Fin-MOSFET or a fin-based junction field-effect transistor (Fin-JFET), respectively. Although the device technologies are still at the early stage of development, 1.2-kV-class WBG gallium nitride (GaN) power Fin-MOSFETs have demonstrated one of the highest static and switching performances in all similarly rated power transistors; UWBG gallium oxide power Fin-MOSFETs have shown high performance up to a breakdown voltage over 2.6 kV. Early UWBG diamond lateral power Fin-MOSFETs have also been demonstrated. Meanwhile, GaN power Fin-JFETs are currently under active development. This article provides a comprehensive tutorial and review of the background and recent advances in WBG and UWBG vertical power FinFETs. It covers fundamental device physics, device and process development, as well as the static and switching performance of various power Fin-MOSFETs and Fin-JFETs. This article is concluded by identifying the current challenges and exciting research opportunities in this very dynamic research field.