Junction Field Effect Transistor Research Articles

3.3-kV 4H-SiC Split-Gate DMOSFET with Floating p+ Polysilicon for High-Frequency Applications

A split-gate metal–oxide–semiconductor field-effect transistor (SG-DMOSFET) is a well-known structure used for reducing the gate–drain capacitance (CGD) to improve switching characteristics. However, SG-DMOSFETs have problems such as the degradation of static characteristics and a high gate-oxide electric field. To solve these problems, we developed a SG-DMOSFET with floating p+ polysilicon (FPS-DMOSFET) and compared it with a conventional planar DMOSFET (C-DMOSFET) and a SG-DMOSFET through Technology Computer-Aided Design (TCAD) simulations. In the FPS-DMOSFET, floating p+ polysilicon (FPS) is inserted between the active gates to disperse the high drain voltage in the off state and form an accumulation layer over the entire junction field effect transistor (JFET) region, similar to a C-DMOSFET, in the on state. Therefore, the FPS-DMOSFET can minimize the degradation of static characteristics such as the breakdown voltage (BV) and specific on resistance (RON,SP) in the split-gate structure. Consequently, the FPS-DMOSFET can shorten the active gate length and achieve a gate-to-drain capacitance (CGD) that is less than those of the C-DMOSFET and SG-DMOSFET by 48% and 41%, respectively. Moreover, the high-frequency figure of merit (HF-FOM = RON,SP × CGD) of the FPS-DMOSFET is lower than those of the C-DMOSFET and SG-DMOSFET by 61% and 49%, respectively. In addition, the FPS-DMOSFET shows an EMOX of 2.1 MV/cm, which guarantees a gate oxide reliability limit of 3 MV/cm. Therefore, the proposed FPS-DMOSFET is the most appropriate device to be used in high-voltage and high-frequency electronic applications.

1.2-kV Vertical GaN Fin-JFETs: High-Temperature Characteristics and Avalanche Capability

This work describes the high-temperature performance and avalanche capability of normally- off 1.2-K V-CLASS vertical gallium nitride (GaN) fin-channel junction field-effect transistors (Fin-JFETs). The GaN Fin-JFETs were fabricated by NexGen Power Systems, Inc. on 100-mm GaN-on-GaN wafers. The threshold voltage ( ${V}_{\text {TH}}$ ) is over 2 V with less than 0.15 V shift from 25 °C to 200 °C. The specific ON-resistance ( ${R}_{ \mathrm{\scriptscriptstyle ON}}$ ) increases from 0.82 at 25 °C to 1.8 $\text{m}\Omega \cdot $ cm2 at 200 °C. The thermal stability of ${V}_{\text {TH}}$ and ${R}_{ \mathrm{\scriptscriptstyle ON}}$ are superior to the values reported in SiC MOSFETs and JFETs. At 200 °C, the gate leakage and drain leakage currents remain below $100~\mu \text{A}$ at −7-V gate bias and 1200-V drain bias, respectively. The gate leakage current mechanism is consistent with carrier hopping across the lateral p-n junction. The high-bias drain leakage current can be well described by the Poole–Frenkel (PF) emission model. An avalanche breakdown voltage ( $BV_{\!\!\text {AVA}}$ ) with positive temperature coefficient is shown in both the quasi-static ${I}$ – ${V}$ sweep and the unclamped inductive switching (UIS) tests. The UIS tests also reveal a $BV_{\!\!\text {AVA}}$ over 1700 V and a critical avalanche energy ( ${E}_{\text {AVA}}$ ) of 7.44 J/cm2, with the ${E}_{\text {AVA}}$ comparable to that of state-of-the-art SiC MOSFETs. These results show the great potentials of vertical GaN Fin-JFETs for medium-voltage power electronics applications.

Epitaxial Al-InAs Heterostructures as Platform for Josephson Junction Field-Effect Transistor Logic Devices

We fabricate Josephson junction field-effect transistors (JJ-FETs) using InAs quantum well heterostructure as the channel, epitaxial Al as superconducting electrodes, and scaled-down Al2O3 gate dielectrics. A systematic investigation of the gate voltage ( ${V}_{{G}}$ ) dependence of the critical current, normal state conductance, and characteristic voltage of the JJ-FETs coupled with capacitance measurements reveals different ${V}_{{G}}$ regimes in the proximity effect characterization of JJ-FETs. Self-consistent Poisson–Schrodinger simulations allow us to associate these ${V}_{{G}}$ regimes with the carriers populating one or more subbands at different vertical locations in the heterostructure. We also discuss the importance of oxide/channel interface quality and its impact on the practical implementation of JJ-FET Boolean logic gates with signal restoration.

Tuning Supercurrent in Josephson Field-Effect Transistors Using h-BN Dielectric.

Epitaxial Al-InAs heterostructures appear as a promising materials platform for exploring mesoscopic and topological superconductivity. A unique property of Josephson junction field effect transistors (JJ-FETs) fabricated on these heterostructures is the ability to tune the supercurrent using a metallic gate. Here, we report the fabrication and measurement of gate-tunable Al-InAs JJ-FETs in which the gate dielectric in contact with the InAs is produced by mechanically exfoliated hexagonal boron nitride (h-BN) followed by dry transfer. We discuss a versatile fabrication process that enables compatibility between layered material transfer and Al-InAs heterostructures that allows us to achieve full gate-tunability of supercurrent by using only 5 nm thick h-BN flakes. Our study shows that pristine properties of epitaxial Josephson junctions, such as product of normal resistance and critical current, IcRn, are preserved. Furthermore, complementary measurements confirm that using h-BN dielectric changes the channel density less when compared to atomic layer deposition of Al2O3.

Fabrication of n‐Type Doped V‐Shaped Structures on (100) Diamond

Herein, a technological process for the fabrication of n‐type doped V‐shaped structures on (100) single‐crystalline diamond substrates, designed to overcome the limitations of n‐type doping on (100) surfaces, is presented. This doping enhancement process can be applied to realize electronic power devices such as a junction barrier Schottky diode or junction field effect transistors with low on‐resistance. Herein, a catalytic etching process is performed by using square‐shaped nickel masks on the diamond surface and annealing in a hydrogen atmosphere, resulting in the formation of inverted pyramidal structures with flat {111} sidewalls. The resulting V‐shaped structures are subsequently overgrown with phosphorus‐doped diamond to achieve n‐type doped facets with higher doping concentrations. Cathodoluminescence studies reveal the predominant incorporation of phosphorus donors on the {111} sidewalls of V‐shaped structures.

Design and investigation of novel ultra-high-voltage junction field-effect transistor embedded with NPN* *Project supported by the National Natural Science Foundation of China (Grant No. 61504049).

Ultra-high-voltage (UHV) junction field-effect transistors (JFETs) embedded separately with the lateral NPN (JFET-LNPN), and the lateral and vertical NPN (JFET-LVNPN), are demonstrated experimentally for improving the electrostatic discharge (ESD) robustness. The ESD characteristics show that both JFET-LNPN and JFET-LVNPN can pass the 5.5-kV human body model (HBM) test. The JFETs embedded with different NPNs have 3.75 times stronger in ESD robustness than the conventional JFET. The failure analysis of the devices is performed with scanning electron microscopy, and the obtained delayer images illustrate that the JFETs embedded with NPN transistors have good voltage endurance capabilities. Finally, the internal physical mechanism of the JFETs embedded with different NPNs is investigated with emission microscopy and Sentaurus simulation, and the results confirm that the JFET-LVNPN has stronger ESD robustness than the JFET-LNPN, because the vertical NPN has a better electron collecting capacity. The JFET-LVNPN is helpful in providing a strong ESD protection and functions for a power device.

AlGaN/GaN-Based Laterally Gated High-Electron-Mobility Transistors With Optimized Linearity

In this work, highly linear AlGaN/GaN laterally gated (or buried gate) high-electron-mobility transistors (HEMTs) are reported. The effect of gate dimensions on source-access resistance and the linearity of laterally gated devices are investigated experimentally in detail for the first time. Transistors with different gate dimensions and conventional planar devices are fabricated using two-step electron beam lithography (EBL). Current–voltage, source-access resistance, small-signal, and two-tone measurements are performed to evaluate the linearity of devices. Contrary to conventional planar HEMTs, the intrinsic transconductance of laterally gated devices monotonically increases with increasing gate voltage, showing a similar behavior as junction field-effect transistors (FETs). The source-access resistance shows a polynomial increase with the drain current, which can be reduced by decreasing the filling ratio of the buried gates. Through the optimization of these two competing factors, i.e., intrinsic transconductance and the source-access resistance, flat transconductance with high linearity is achieved experimentally. The laterally gated structure shows flat transconductance and small-signal power gain over a larger span of gate voltage that is 2.5 times higher than a planar device. Moreover, 6.9-dB improvement in output intercept point (OIP3)/ ${P}_{\text {DC}}$ is achieved. This approach can be used to improve the linearity of AlGaN/GaN HEMTs at the device level.

High Noise Margin, Digital Logic Design Using Josephson Junction Field-Effect Transistors for Cryogenic Computing

As compute demands and their large energy costs continue to rise in the datacenter, it is imperative to identify low energy compute solutions. One approach is to investigate device schemes based on collective mode phenomena arising at low temperatures where power dissipation and switching voltage can be extremely low. Additionally, such devices could also have applications in quantum computing where such a low power logic/memory scheme could possibly be integrated onto the qubit plane, which is typically at ~10 mK temperature. Josephson Junction Field Effect Transistor (JJFET) is a promising candidate for low power operation with zero voltage drop across its drain-source terminals while operating in the superconducting regime. JJFET logic gate is typically realized as a n-type JJFET connected in a common-source configuration with a current source load. This results in high noise margin for logic-1 input but not for both logic-1 and 0. In this paper, we propose an overdamped region, n-type JJFET based digital logic using a cascaded common-source configuration-based design yielding high noise margin for both the logic inputs. DC noise margin sensitivity analysis is performed for the bias current and threshold voltage modulation. The noise margin can be further improved (approaches ideal inverter case) by cascading multiple common source stages yielding higher inverter gain.

A novel GaN vertical junction field-effect transistor with intrinsic reverse conduction capability and kilo-volt breakdown voltage

In this work, a novel GaN vertical junction field-effect transistor (JFET) with intrinsic reverse conduction capability (RC-JFET) is proposed and studied by simulation. The RC-JFET features two separate source electrodes, one of which performs as an embedded freewheeling diode that can enable the reverse conduction function of the device. Benefiting from a structure with two separate source electrodes, the forward and reverse current conduction paths are also separated, which allows us to independently design the forward and reverse conduction characteristics of the RC-JFET. The forward threshold voltage V TH is 1.6 V while the reverse turn-on voltage V on,rev is as low as 0.7 V. In addition, the buried floating p-base can effectively modulate the E-field in the GaN drift region, which can achieve a high breakdown voltage of 1720 V with an R on,sp of 2.79 mΩ cm2. Due to the embedded freewheeling diode, the device exhibits a short reverse recovery time T rr of 13 ns. By featuring an intrinsic reverse conduction capability, the proposed RC-JFET is capable of eliminating the externally connected diode, which is beneficial for improved switching speed and switching power loss due to the reduction of parasitic effects and chip size of power circuits.

The Special Features of Simulation of the Current–Voltage Characteristics of JFETs in the Cryogenic Temperature Range

The compact models of junction field effect transistors (JFETs) used in release-quality versions of SPICE-like programs are focused only on the standard temperatures ranging from –60 to 150°C and are unworkable for an electronic circuit design in the cryogenic temperature range (below –120°C). It this study, the Low-T SPICE model of the JFET for designing electronic circuits in the extended temperature range, including the cryogenic range (from –200 to 110°С), is proposed. The model takes into account the changes in the I–V curves caused by the effect of ultralow temperature: growth of the saturation voltage VD sat, decrease of the pinch-off current Ip and steepness BETA, negative slope LAMBDA of the output I–V curves, increase of the drain–source resistance RD as the result of the freezing effect, etc. For this purpose, the dependences of the specified parameters on temperature are introduced in the model. The procedure for extracting the SPICE parameters of the Low-T SPICE model of the JFET is developed according to the results of the measurements of the standard set of the I–V curves in the cryogenic temperature range. The error of the calculation of the I–V curves is not higher than 10–15% in the temperature range from –200 to 110°C.

Device and Circuit Design for Improving the Freewheeling Characteristics of High Voltage Monolithic Integrated Circuit

In this article, a new freewheeling circuit with a junction field-effect transistor (JFET) structure is developed to replace the traditional high voltage diode for freewheeling in the high voltage monolithic IC for the first time. The JFET structure has its pinch-off voltage lower than 40 V, and it can sustain the reverse voltage higher than 500 V in off-state. Adopting the new freewheeling circuit, the reverse recovery charge (Q <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RR</sub> ) and the peak reverse recovery current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RRM</sub> ) is decreased boffy about 89.5% and 33.6%, respectively, when the load current is 0.5 A. Based on the proposed freewheeling circuit, a deadtime control circuit is also developed in this article. By employing that control circuit, it is no need to detect the output signal state of the counter channel before controlling the deadtime, therefore the deadtime could be designed as small as possible to decrease the freewheeling loss. In this article, the high voltage monolithic IC is implemented by thick layer silicon on insulator technology. All the new devices and circuits are compatible with the technology for the traditional monolithic IC without any additional process.

High-Performance van der Waals Junction Field-Effect Transistors Utilizing Organic Molecule/Transition Metal Dichalcogenide Interface.

Two-dimensional (2D) transition metal dichalcogenide (TMD) hetero PN junctions with a van der Waals (vdW) interface have received much attention, because PN diodes are basically important to control the vertical current across the junction. Interestingly, the same vdW PN junction structure can be utilized for junction field-effect transistors (JFETs) where in-plane current is controlled along the junction. However, 2D vdW JFETs seem rarely reported, despite their own advantages to achieve when good vdW junction is secured. Here, we present high-performance p-MoTe2 JFETs using almost perfect vdW organic Alq3/p-MoTe2 junctions and demonstrate organic NPB/n-MoS2 JFETs. The p- and n-channel JFETs stably show high mobilities of 60-80 and ∼800 cm2/V s, respectively, along with a high ON/OFF current ratio (>1 × 105) and minimal gate leakage at 5 V even after a few months. Such performances are attributed to a quality vdW junction at organic layer/TMD interfaces.

Low-Noise Si-JFETs Enhanced by Split-Channel Concept

We present the results of low-noise silicon junction field-effect transistors (JFET) with a split-channel concept. The device can be manufactured as a module in a standard CMOS process. The channel is split under the top gate of the JFET into a source-side main channel and a drain-side-extended drain channel. Devices with design gate length between 1.0 and 3.0 μm and effective channel length between 0.1 and 2.2 μm were fabricated. It is shown that transconductance and channel resistance are dominated by the overlap between the main channel and the top gate. Output resistance can be enhanced by increasing the overlap of the extended drain channel with the top gate. A cutoff frequency of up to 2.5 GHz, 60-mS/mm maximum transconductance, and an intrinsic gain of 2200 were achieved. For the main channel length below 1 μm, a strong roll-off behavior of the threshold voltage is observed. The flicker-corner frequency for 1/f noise is 500 Hz. Above 1 kHz, √ a value of 2.5-nV/ Hz input-referred voltage noise density at 0.3-pF input capacitance was achieved. Also, a brief comparison to devices from other publications is presented.

Lateral depletion-mode 4H-SiC n-channel junction field-effect transistors operational at 400 °C* *Project supported by the Key Research and Development Program of Shaanxi Province, China (Grant No. 2020ZDLGY03-07), the National Science Foundation of China (Grant Nos. 61774117 and 61774119), the Science Challenge Project (Grant No. TZ2018003), the National Key R&D Program of China (Grant No. 2017YFB0102302), the Shaanxi Science & Technology

This paper presents the development of lateral depletion-mode n-channel 4H-SiC junction field-effect transistors (LJFETs) using double-mesa process toward high-temperature integrated circuit (IC) applications. At room temperature, the fabricated LJFETs show a drain-to-source saturation current of 23.03 μA/μm, which corresponds to a current density of 7678 A/cm2. The gate-to-source parasitic resistance of 17.56 kΩ ⋅ μm is reduced to contribute only 13.49% of the on-resistance of 130.15 kΩ ⋅ μm, which helps to improve the transconductance up to 8.61 μS/μm. High temperature characteristics of LJFETs were performed from room temperature to 400 °C. At temperatures up to 400 °C in air, it is observed that the fabricated LJFETs still show normally-on operating characteristics. The drain-to-source saturation current, transconductance and intrinsic gain at 400 °C are 7.47 μA/μm, 2.35 μS/μm and 41.35, respectively. These results show significant improvement over state-of-the-art and make them attractive for high-temperature IC applications.

Free Carrier Mobility, Series Resistance, and Threshold Voltage Extraction in Junction FETs

In this brief, extraction methods are proposed for determining the essential parameters of double gate junction field-effect transistors (FETs). First, a novel method for determining free carrier effective mobility, similar to a recently proposed method for MOSFETs, is developed. The same method is then extended to cover also the case when series resistance is present, while series resistance itself may be determined from the measurement from two FETs with different channel lengths. The key technological and design parameter is the threshold voltage, which may be unambiguously determined from the transconductance-to-current ratio with a constant-current method. The new methods are shown to be effective over a wide range of technical parameters, using technology computer-aided design simulations.

M-Learning Based Remote Laboratory for Electronics Experiments

&lt;p&gt;The paper goals on the implementation of Mobile learning (M-learning) based Remote Laboratory to maximize the available resource as well as to improve self learning ability. The developed system provides practical experience to the learners in the field of analog electronics. This laboratory permits the learners to conduct experiments on real time with the internet facility using developed android mobile application. A characteristic of Junction Field Effect Transistors (JFET’s) related to analog electronics has been considered for remote laboratory experimentation. The designed system can be expanded by adding new experiments without any complexity. This M-learning based remote laboratory approach enables the sharing of resource between the institutions for the minimization of expense and also encourages learners by enhancing engineering education.&lt;/p&gt;

GaN Vertical-Channel Junction Field-Effect Transistors With Regrown p-GaN by MOCVD

We report an experimental demonstration of GaN-based vertical-channel junction field-effect transistors (VC-JFETs). A p-GaN regrowth by metalorganic chemical vapor deposition (MOCVD) and a subsequent self-planarization process were developed to fabricate the GaN VC-JFETs. Fin-like channel regions were patterned by electron beam lithography (EBL) and aligned to ${m}$ -plane or ${a}$ -plane. The electrical properties of lateral and vertical p-n junctions were characterized to verify the effectiveness of the p-GaN regrowth. Both VC-JFETs with ${m}$ -plane and ${a}$ -plane channels show decent gate modulation. We further discussed important factors that may affect the device performance including interfacial impurities and nonuniform acceptor distribution. This work highlights the successful demonstration of GaN VC-JFETs and lateral p-n junctions by an etch-then-regrow process, providing valuable information and reference for the further development of GaN power electronics.

Technological and devices modeling of complementary JFETs over a wide temperature range

The article presents the results of process and device modeling results of complementary junction field-effect transistors (JFET). The models necessary for calculating the JFET in the temperature range down to cryogenic were described: the Klaassen model of the carriers mobility (Phillips company model) and Shockley-Read-Hall recombination model, taking into account the doping dependence, Lackner's model of avalanche multiplication, Fermi-Dirac statistics, Slotboom model, designed to describe the dependence of the band gap on the doping concentration. These models take into account the effect of temperature. We have described in detail the model of incomplete ionization of an impurity, which determines the concentration of charge carriers at cryogenic temperatures. The TCAD-based JFET self-heating effect is simulated using a simplified model that significantly reduces the calculation time compared to the thermodynamic model. Studies on the selection of an algorithm for calculating a system of differential equations in the temperature region are carried out. It is shown that the SLIP90 algorithm provides calculations in the entire temperature range down to T = 25 K. The article shows that modification of the design can significantly affect the choice of calculation algorithm. The dependences of the main JFET parameters are analyzed taking into account the selected models on temperature and constructive and technological solutions are proposed to reduce the influence of ultra-low temperatures on the parameters of complementary JFETs.The research results showed that reducing the cut-off voltage reduces the influence of temperature on the shorted-gate drain current JFET in the temperature range. At the same time, n-channel transistors have advantages in terms of a smaller change in parameters over the temperature range down to the temperatures at which the “freezing out” of the impurity charge carriers begins. Several types of transistor topologies were simulated in the temperature range, which showed that the value of the shorted-gate drain current increases linearly with the number of gates. However, there are differences in the dependence of the main parameters in the temperature range depending on the design of the layers of complementary JFETs. Using the emitter region as the top gate weakly affects the parameters of the n-channel JFET in the case of the formation of complementary JFETs in the microwave complementary bipolar technological process, and for the p-channel JFET the temperature stability of the parameters deteriorates. For the p-channel transistor with a gate based on the base region, the temperature stability over the range ΔT = 150–330 K of the shorted-gate drain current is higher than for the transistor with a gate based on the emitter. For the n-channel transistor, the dependence is inverse. Over the range ΔT = 150–77 K, the dependence of the parameters of the transistors for two structures does not differ. In principle, the results show that the change in the ambient temperature has a greater effect on the p-channel transistor than on the n-channel.

Nonvolatile Associative Memory Design Based on Spintronic Synapses and CNTFET Neurons

Many advances have been made in developing bio-inspired intelligent systems for performing important tasks like pattern association, which cannot be performed effectively by the conventional computer architectures. This paper presents a novel nonvolatile associative memory based on spintronic synapses utilizing magnetic tunnel junction (MTJ) and carbon nanotube field-effect transistors (CNTFET)-based neurons. MTJs introduce fascinating features like reconfigurability, nonvolatility, and high endurance to the design, while CNTFETs compensate for the flaws of the conventional transistors in deep nanoscale nodes. The comprehensive simulations validate the functionality of the proposed synaptic cell, and neuron, even in the presence of major process variations. The application of the proposed synaptic cell and neuron in the hardware realization of multi-associative memories is also investigated. The simulation results indicate that the proposed hardware-based multi-associative memory performs similar to its ideal software-based counterpart with a less than 3 percent difference in the successful recall rate. It also noteworthy that since the input and output of the proposed design are logical &#x2018;0&#x2019; and &#x2018;1&#x2019;, the proposed design does not need any extra component for voltage conversion.

Design of Ion-Implanted Junction Termination Extension for Vertical GaN Pin Rectifiers

Gallium-nitride and related materials have become suitable semiconductor platforms for next-generation power electronic devices. This materials system leverages unique properties of wider energy bandgap, higher carrier mobility, and ultrashort carrier recombination lifetime to achieve much improved bipolar switching characteristics when compared to Si- or SiC-based counterparts. In recent years, vertical GaN switches such as PIN rectifiers, junction barrier Schottky (JBS) diodes, and junction field-effect transistors (JFETs) have been actively sought in hopes to achieve low-loss device performance at kilo-volt (kV) operation range. Over the years, significant progresses in low-defect-density substrate preparation and high-quality epitaxial growth using metalorganic chemical vapor deposition (MOCVD) reactors, along with robust fabrication processing techniques helped achieve many impressive GaN-based power device demonstrations. As vertical GaN devices operate at the kV ranges, proper engineering of the electric field is a key to exploiting the ultimate device performance. To this end, several device-level design strategies such as field plates, beveled sidewalls, and junction termination extensions have been studied. In the context of realizing a planar device topology in GaN materials systems, ion implantation into GaN materials systems offer new opportunities to provide precise control of inhomogeneous carrier distribution for the creation of versatile doping profiles and geometries such as selectively doped regions or highly resistive regions at arbitrary locations in GaN devices.In this presentation, we will discuss a study of the floating guard rings (FGRs) designs that utilize a nitrogen-ion implantation isolation technique. The designs can effectively mitigate the electric field crowding effect and enable robust avalanching capability in vertical GaN PIN rectifiers. Using 1.2-kV GaN PIN rectifiers as design examples, a set of numerical simulation study was performed using a TCAD-Sentaurus software package. The results showed that a closely packed FGRs with a gap of adjacent FGRs in the range of 1-3 microns, a width of the FGRs in the range of 4 to 6 microns, along with a variable-width FGR design toward the outer rings can effectively suppress the peak electric field distribution at edge of the main junction and the surface of junction termination extensions. For example, consider a GaN PIN rectifier structure with a drift layer that consists of 6 microns of unintentionally doped (UID) GaN (n= 5×1015 cm-3) and a 4-micron-thick lightly doped GaN (n = 2×1016 cm-3). The FGR structures can be formed by creating highly resistive GaN regions in the epitaxially grown p-GaN layer using an ion implantation technique. In this design, five of the FGRs have 1-micron-wide undoped GaN and a 6-micron-wide p-GaN region in the p-GaN layer. The outermost FGR (the 6th FGR) is designed to have a 2-micron-wide undoped GaN and 5-micron-wide p-GaN extension. The resulting field distribution showed an effective suppression of the field crowding effect at the edge of the main junction (Figure 1(a)) and a smooth electric potential drop along the lateral direction can be achieved (Figure 1(b)). As shown in Figure 2, the electric field distribution at the vertical junction was plotted for two FGR designs with and without a metal plate on top of the p-GaN region. The electric field distribution of the main junction was also plotted for comparison. It is clearly shown that the peak electric field at the vertical junction is effectively reduced with the metal-plated FGRs by >10% when compared to a non-plated FGRs. Reduced peak electric field in typically high-electric-field regions can safeguard the device from experiencing premature breakdown for robust switching operations. We found that 6 FGRs with a total lateral extension of <45 microns from the main pn junction are sufficient to provide effective junction termination for 1.2 kV devices. Such designs could also support for devices with a blocking voltage up to 1.6 kV.FGR designs were implemented in GaN PIN rectifiers for experimental validation. The fabrication processing of vertical GaN PIN rectifiers was grown on n-type free-standing or bulk GaN substrates using a MOCVD reactor. The cathode was formed by depositing Ti/Al-based ohmic contact on the backside of the wafer, and the anode electrode was formed on the topside p-type GaN layer. Nitrogen-ion implantation was employed to create FGR structures and served as a mean of inter-device isolation. Detailed design strategies of the FGRs, device processing and device characterizations will be discussed in the conference. Figure 1