Junction Doping Profile Research Articles

Low VπLπ and Driving Voltage Interleaved Silicon Phase Shifter for Modulation Applications

Interleaved doped Mach-Zehnder Modulators (MZMs) are one solution to attaining higher modulation efficiencies compared with lateral junction structures, due to greater modal overlap with the depletion regions of the PN junctions. In this work, we present an interleaved Si modulator device design and process simulation based on a three-step ion implantation process that aims to obtain a realistic PN junction doping profile using a Monte Carlo simulation method. A high doping concentration on the order of 5×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">18</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−3</sup> for the P and N regions is explored. Device simulations to track the carrier motion under different voltage biases are performed. Using equivalent medium theory, we calculated the modulation efficiency V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">π</sub> ·L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">π</sub> of the interleaved Si modulator to be 0.19 V·cm under 1V reverse bias. This work is among the highest reported modulation efficiencies thus far in MZMs without photonic resonance structures.

Dual-gate operation and carrier transport in SiGe p–n junction nanowires

We investigate carrier transport in silicon–germanium nanowires with an axial p–n junction doping profile by fabricating these wires into transistors that feature separate top gates over each doping segment. By independently biasing each gate, carrier concentrations in the n- and p-side of the wire can be modulated. For these devices, which were fabricated with nickel source–drain electrical contacts, holes are the dominant charge carrier, with more favorable hole injection occurring on the p-side contact. Channel current exhibits greater sensitivity to the n-side gate, and in the reverse biased source–drain configuration, current is limited by the nickel/n-side Schottky contact.

High performance Ge ultra-shallow junctions fabricated by a novel formation technique featuring spin-on dopant and laser annealing for sub-10 nm technology applications

In this work, we explored a novel technique for the formation of ultra-shallow p+/n and n+/p junctions on Ge substrate using the spin-on dopant (SOD) followed by laser annealing (LA). The junction depth and doping profiles were extracted and compared between Ge junctions activated by LA and by the conventional rapid thermal annealing (RTA). It is experimentally confirmed that the process of SOD followed by LA method outperformed that by RTA technique in terms of the ultra-shallow junction depth, higher surface doping concentration and steeper doping profiles. Therefore, the high performance Ge p+/n and n+/p junctions fabricated by SOD followed by LA method exhibit suppressed junction leakage current and raised on/off ratios, making this novel technique a promising way for source/drain formation in future technology nodes.

Low-Noise Avalanche Photodiode With Graded Junction in 0.15-&lt;inline-formula&gt; &lt;tex-math notation="TeX"&gt;$\mu{\rm m}$ &lt;/tex-math&gt;&lt;/inline-formula&gt; CMOS Technology

This letter presents the experimental characterization and noise modeling of a CMOS avalanche photodiode with pwell/n-iso active junction fabricated in a 0.15-μm standard CMOS process. The device exhibits a remarkably low excess noise factor F = 6 at a gain M = 50 in the blue spectral region, and F = 12 at M = 50 in the near-infrared. Gain and noise characteristics are accurately predicted using Hayat dead-space model applied to a linearly graded junction doping profile.

Source Doping Profile Design for Si and Ge Tunnel FET

The source junction doping profile design for Si and Ge tunnel FET (TFET) is discussed and compared in this paper. By using Sentaurus TCAD tools with calibrated dynamic non-local band-to-band tunneling and non-local trap-assisted-tunneling models, it is shown that when Si TFET’s source doping gradient increases from 1.5 to 15 nm/dec, due to the gradual band bending and lower electric field at tunnel junction, average subthreshold slope (SS) increases from 38 to 64 mV/dec, onset voltage increases by 0.1 V and ON-current decreases by almost one decade. Although Ge TFET has larger tunneling electric field, the doping profile impact on SS is more severe than that of Si TFET. The design margin for doping profile under different gate length, gate oxide thickness and source-gate overlap is also discussed. Results show that for short channel Si TFETs, doping profile design margin for SS below 60mV/dec decreases as gate length shortens. For short channel Si TFETs design, the process requirement of abrupt source doping profile can be relaxed if thin gate oxide and a small underlap at the source junction are employed, and more stringent process control is required for Ge TFETs.

Surface Potential Measurements of Reconfigurable p-n Junctions in Graphene

The direct surface potential measurement of reconfigurable graphene p-n junctions in exfoliated graphene deposited on a buried split-gate test structure is reported. The experimental geometry permitted direct imaging of the Fermi level variation across the electrostatically-doped p-n junction using Kelvin Probe Force Microscopy (KPFM). The measured graphene p-n junction doping profile and junction width are in good agreement with predictions from finite-element calculations.

Minimization of Gate-Induced Drain Leakage by Controlling Gate Underlap Length for Low-Standby-Power Operation of 20-nm-Level Four-Terminal Silicon-on-Insulator Fin-Shaped Field Effect Transistor

Recently, gate-induced drain leakage (GIDL) has become a crucial factor of current characteristics as junction doping concentration becomes more abruptly graded owing to device scaling. It should be effectively suppressed for the low-standby-power operation of ultra small metal–oxide–semiconductor field effect transistor (MOSFET) devices. In this work, the appropriate underlap length range for the effective minimization of GIDL in 20-nm-level four-terminal (4-T) fin-shaped FET (FinFET) on silicon-on-insulator (SOI) is established. In order to identify the effect of underlap length on GIDL more precisely, the source and drain (S/D) junction doping profile and the majority/minority carrier lifetimes have been extracted by the measurement of a p–n junction test element group (TEG). The TEG was fabricated under the same process conditions that were used in forming the S/D junctions of 100-nm-level 4-T SOI FinFET in our previous research. The GIDL component in the off-state current is investigated with underlap length variation along with the inspection of basic current characteristics. For low-standby-power operation, an underlap junction is more desirable than an overlap junction, and the underlap length should be at least 10 nm to suppress GIDL effectively.

Performance and Modeling of the MWIR HgCdTe Electron Avalanche Photodiode

The operation of the mid-wave infrared (MWIR) HgCdTe cylindrical electron injection avalanche photodiode (e-APD) is described. The measured gain and excess noise factor are related to the collection region fill factor. A two-dimensional diffusion model calculates the time-dependent response and steady-state pixel point spread function for cylindrical diodes, and predicts bandwidths near 1 GHz for small geometries. A 2 μm diameter spot scan system was developed for point spread function and crosstalk measurements at 80 K. An electron diffusion length of 13.4 μm was extracted from spot scan data. Bandwidth data are shown that indicate bandwidths in excess of 300 MHz for small unit cells geometries. Dark current data, at high gain levels, indicate an effective gain normalized dark density count as low as 1000 counts/μs/cm2 at an APD gain of 444. A junction doping profile was determined from capacitance–voltage data. Spectral response data shows a gain-independent characteristic.

On the Role of the N–N$^{+}$ Junction Doping Profile of a PIN Diode on Its Turn-Off Transient Behavior

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> This paper focuses on the role of the N–N<formula formulatype="inline"> <tex>$^{+}$</tex></formula> junction doping profile model of a PiN diode on its turn-off transient and, particularly, the influence of multiple epitaxies in the N–N<formula formulatype="inline"><tex>$^{+}$</tex></formula> profile. A conventional doping profile model has been used in a previous work and an identification procedure for the main design parameters has been demonstrated. However the validity range of identified PiN-diode models appeared quite limited for hard current and voltage conditions. Readers have asked for the effect of a more advanced doping profile. The turn-off transient of an STTB506D device is considered from experimental and simulation point-of-view inside a fully characterized switching cell. A limitation of the conventional doping profile model is demonstrated and explained physically in order to introduce the necessity of a more complex doping profile. An advanced doping profile is then considered and a comparative study between experimental and simulated turn-off transient behavior of the device is established. </para>

Analyses on Current Characteristics of 3-D MOSFET Determined by Junction Doping Profiles for Nonvolatile Memory Devices

One of 3-D devices to achieve high density arrays was adopted in this study, where source and drain junctions are formed along the silicon fin. The screening by adjacent high fins for large sensing margin makes it hard to ion-implant with high angle so that vertical ion implantation is inevitable. In this study, the dependency of current characteristics on doping profiles is investigated by 3-D numerical analysis. The position of concentration peak and the doping gradient are varied to look into the effects on driving currents. Through these analyses, the optimum condition of ion implantation for 3-D devices is estimated.

Accurate channel length extraction by split C-V measurements on short-channel MOSFETs

This paper investigates the extraction of channel length from split current-voltage (C-V) measurements of small gate length PMOS transistors. Using device simulations, including quantum-mechanical effects, scanning spreading resistance measurements, and process simulations, the authors correlate the variation of the overlap capacitance with the gate voltage, and the length of the lateral junction doping profile. It is suggested that an accurate extraction of the metallurgical and effective gate length can be obtained from C-V measurements subtracting the overlap capacitance at V/sub G/=V/sub FB/ and V/sub G/=V/sub FB/+0.8V.

Boron diffusion in amorphous silicon and the role of fluorine

We demonstrate that boron diffuses at high concentrations during low-temperature thermal annealing in amorphous silicon pre-amorphized by germanium ion implantation. For a typical boron ultrashallow junction doping profile, concentrations as high as 2×1020 cm−3 appear to be highly mobile at 500 and 600 °C in the amorphous silicon region before recrystallization. In crystalline silicon at the same temperatures the mobile boron concentration is at least two orders of magnitude lower. We also show that boron diffusivity in the amorphous region is similar with and without fluorine. The role of fluorine is not to enhance boron diffusivity, but to dramatically slow down the recrystallization rate, allowing the boron profile to be mobile up to the concentration of 2×1020 cm−3 for a longer time.

Impact of Localized Channel and Field Implantation on Data Retention Time for Gigabit Density DRAM Technology

As the density of dynamic random access memories (DRAMs) enters into giga-bit regime with deep sub-quarter-micrometer feature size, the control of junction leakage current at storage node becomes much more important because of increased channel doping concentration. In this paper, we analyzed the junction leakage current of cell transistor and suggested effective cell structure to improve the data retention time for mass-produced 512 Mb DRAM with 0.12 μm. This cell structure, which is based on localized channel and field implantation, reduces the junction leakage current by relaxing junction doping profile and implantation damages at source and drain regions. The relaxed junction profile can reduce the electric field strength of a junction and thus improve data retention time in DRAMs. In addition, subthreshold characteristics of a cell transistor are improved dramatically with this scheme by increasing threshold voltage of corner transistor that is generally lowered by boron segregation and field crowding at the shallow trench isolation boundary in the conventional cell transistor. The proposed approach reduced the cumulative fail-bit probability by about 80% at the data retention time of 128 ms and possibly, can be applied to future high density DRAMs with feature size down to 0.1 μm range. © 2003 The Electrochemical Society. All rights reserved.

An analytical model for space-charge region capacitance based on practical doping profiles under any bias conditions

An analytical model is presented for quasi-static capacitance of the space-charge region in a p–n junction. The model is valid for realistic junction doping profiles under any bias conditions. It consists of local models in three bias regions. For the high-reverse bias region, a novel analytical model is derived. For the moderate-bias region, an empirical model commonly used in SPICE is adopted. Finally, for the high-forward bias region, the junction profiles are approximated by linearly-graded junctions. Existing analytical models are then modified appropriately to characterize both high-injection and heavy-doping effects for advanced bipolar transistors. Compared to previously developed analytical models or existing empirical models, as well as numerical simulation results, the analytical model presented here shows an improved accuracy and therefore provides a better tool for both device and circuit simulations.

Elevated n/sup +//p junctions by implant into CoSi/sub 2/ formed on selective epitaxy for deep submicron MOSFETs

Very shallow elevated n/sup +//p junctions formed by arsenic implant into or through cobalt silicide (CoSi/sub 2/) formed on selective epitaxial layers and their application to deep submicron n-channel MOSFETs were studied for the first time. PREDICT 1.6 simulation program was employed to choose the desired implant energies and annealing thermal cycle based on theoretically predicted silicide thickness. The implanted CoSi/sub 2/ elevated junctions had low reverse current and no bias voltage dependence up to 5 V. Diffusion current dominated the junction forward current, and good ideality factors close to 1 were obtained. A nearly abrupt junction doping profile was achieved. Deep submicron n-channel MOSFETs incorporating implanted CoSi/sub 2/ elevated junctions were demonstrated. Sharp turn-off and reasonably large drain currents were achieved.

Phase modulation nonlinearity of double-heterostructure p-n junction diode light modulators

The phase modulation due to the linear electro-optic effect of GaAs–AlxGa1−xAs double-heterostructure (DH) p-n junction diode light modulators can be a strong function of the applied bias voltage. The observed nonlinear voltage dependence of the phase difference Δφ between the phases of the TE and TM modes is in good agreement with the predictions of a mathematical dielectric slab waveguide model with five stepwise constant dielectric layers, if a suitably defined average junction electric field is used. The magnitude of Δφ and its nonlinear voltage dependence measurably depend on the properties of the optical dielectric waveguide and on the p-n junction doping profile. Within the accuracy of our measurements, we have not been able to identify contributions due to higher-order electro-optic effects. Our results emphasize that large modulation effects and good modulation linearity of Δφ modulation can be achieved by appropriately controlled p-n junction doping profiles. Conversely, Δφ measurements as a function of bias provide a novel tool for studying p-n junction doping profiles and for determining the Al concentration of the AlxGa1−xAs layers of DH diodes.

Bipolar Transistor Screening Methods for Neutron Hardness Assurance

A detailed bipolar transistor model has been developed to determine the dependence of post-irradiation electrical parameters on preirradiation electrical measurements and physical parameters. Some of the features of the model are the following: (a) Postirradiation lifetimes vary with injection level. (b) Electric fields in base and emitter regions increase the emitter efficiency and normal base transport factor. (c) Collector resistance decreases when minority carriers are injected into the collector. (d) Collector resistance decreases when the collector-base junction is reverse biased and the depletion region extends into the collector. (e) Junction doping profiles are modeled as exponential-constant. (f) Junction efficiency degrades as injection level increases. (g) Base width varies with collector-base voltage. (h) All parameters except emitter width and junction areas are determined from electrical measurements, and radiation damage constants are determined from postirradiation parameters. The radiation damage constants are utilized in calculating sensitivity parameters for preirradiation parameters to be used for neutron hardness screening. A computer program varies selected preirradiation model parameters one at a time and the resulting change in an electrical parameter of interest at a specified neutron fluence is determined. The postirradiation performance of other devices of the same type at the same operating point and irradiation level can be predicted as follows: (1) Multiply the appropriate sensitivity parameter by the normalized deviation of each screening parameter from the corresponding reference unit value: (2) add the sum of these products to unity; (3) multiply this quantity by the post-irradiation electrical parameter of the reference unit.

A Technique for Determining p-n Junction Doping Profiles and Its Application to GaP

A technique for determining p-n junction doping profiles is presented. The doping level distribution is determined from a series of surface-barrier capacitance (SBC) measurements, using the recently developed continuous impurity plotter (CIP) [J. A. Copeland, IEEE Trans. Electron Devices ED-16, 445 (1969)]. The SBC measurements are made on an array of Schottky barrier diodes deposited on a 3° angle-lapped junction. The effective spatial resolution normal to the junction is 5 μ. This method yields a higher resolution than the four-point probe method, requires less time than the step layer capacitance technique, and is more accurate than either method. In general, it is the most efficient approach to determining accurate junction impurity profiles presented to date. To illustrate the utility of the technique, an impurity doping profile is determined for an n-on-p liquid-phase epitaxy GaP diode.