Abstract
This paper investigates the extraction of channel length from split current-voltage (C-V) measurements of small gate length PMOS transistors. Using device simulations, including quantum-mechanical effects, scanning spreading resistance measurements, and process simulations, the authors correlate the variation of the overlap capacitance with the gate voltage, and the length of the lateral junction doping profile. It is suggested that an accurate extraction of the metallurgical and effective gate length can be obtained from C-V measurements subtracting the overlap capacitance at V/sub G/=V/sub FB/ and V/sub G/=V/sub FB/+0.8V.
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