Evaluation of Effective Gate Length of Gallium Arsenide Metal-Semiconductor Field Effect Transistors

Abstract

To improve the performance of field-effect transistors (FETs), it is necessary to reduce the gate length. However the gate length, which affects the characteristics of FETs, is generally not the same as the metallurgical gate length, and is referred to as the effective gate length, which depends on the device structure. This paper describes a method of evaluating the effective gate length of GaAs MESFETs using I–V measurement under the bias condition, then discusses the relationship between the effective gate length and the structural parameters of the device, such as the distance between the gate metal and the n+ region, which is controlled by the sidewall thickness for n+ self-alignment ion implantation. From the results of a two-dimensional device simulation, it is observed that the effective gate length is related to the depletion layer extending around the gate electrode.