Johnson Counter Research Articles

An 8-bit TDC implemented with two nested Johnson counters

This work presents a Time-to-Digital Converter implemented using two nested Johnson counters and suitable for time-lapse measurement applications. The proposed structure is composed of two 4-bit nested counters, two digital-logic control networks, two registers and a single decoder. Semi-dynamic logic was used for the decoder to reduce its power consumption. The system has a standard digital output and is powered by a 1.8 V supply with a total power consumption of 32.4 mW. A prototype was fabricated using a TSMC 180 nm CMOS technology. The proposed structure uses a 508 µm x 225 µm area. In addition, this TDC has a standard deviation of 0.78 LSB with a fixed input time interval operating at a frequency of 1 MHz. The proposed structure shows good performance results and repeatability for continuous conversion conditions, these results are attributed to the simplicity of the system and the use of counters with minimum gate delay as the main elements for the TDC.

Performance Enhancement Counter with Minimal Clock Period

A synchronous binary counter is a fundamental component in VLSI design which are used commonly. synchronous binary counter is fast and are used in many applications as it supports wide bit-width. Due to large fan-outs and long carry chains many previous counters have low counting rate when the size of the counters is large. A new fast structure has been suggested for synchronous binary counter with a very low delay for counter with size ranging from 8 to 128 bits. To reduce the complexity of hardware a 1-bit Johnson counter has been used and then duplicate it to minimise propagation delay induced by large fan-outs. The suggested design is realised with a small number of flip-flops, using a back carry propagation counter and a counter based on state look ahead logic, which reduces power and delay.

64 Bit Binary Counter with Minimal Clock Period

Novel rapid formations of synchronous binary counting with single minimum period of counting for practical counters are developed in this project. A synchronous binary counter is required in many applications since it is rapid, also can help a broad bit-width. Basically, because of massive fan-outs and extensive carry chains, earlier counters have a limited counting rate, mainly when size of the counter is not modest. It employs a single bit Johnson counter to decrease whole hardware complications, then copy it to lessen the propagation latency caused by huge fan-outs. In this paper, re programmable the clock utilized in it for various applications functioning at different clock rates and there’ll be a variation within the delay values because the clock is reprogrammed the critical may varies for various rates. The counter output results are obtained for various bit up to 64 and therefore the design provides various clock rates with variations in area and delay.

Design of all-optical Johnson counter using SOA-MZI at 100 Gb/s

All-optical networks utilize optical memory elements as the basic building blocks for optical signal processing and for providing high performance computing applications. In this communication, we propose and realize an integrable scheme for the design of all optical Johnson counter utilizing D flip flops (DFFs). All optical counter have been designed using cascaded DFFs memories and a single clock pulse have been applied as input to the counter. The DFF has been implemented by employing semiconductor optical amplifier - Mach Zehnder Interferometer (SOA-MZI) based all optical NAND and NOT gates. The performance of the device has been investigated in terms of extinction ratio, Q factor, amplitude modulation and contrast ratio verifying its operation at 100 Gb/s.

Constant-Time Synchronous Binary Counter With Minimal Clock Period

A synchronous binary counter is one of the basic components widely used in VLSI design, and it is required to be fast and support a wide bit-width in many applications. However, most of the previous counters are associated with a limited counting rate due to large fan-outs and long carry chains, especially when the counter size is not small. This brief proposes a new fast structure for synchronous binary counting, which has a minimal counting period for practical counter sizes ranging from 8 to 128 bits. We first adopt an 1-bit Johnson counter to reduce the overall hardware complexity, and then duplicate the 1-bit Johnson counter to decrease the propagation delay caused by large fan-outs. Implementation results show that the proposed design can be realized with a small number of flip-flops, which is almost linear to the counter size, and it operates at a clock frequency of 2GHz in a 65nm CMOS technology, being limited only by the counting rate of the least significant bit.

Analysis and optimal design of johnson counter

The power consumption and propagation delay in a digital system is mainly due to sequential circuits. VLSI designers were primarily focused with low power, decreased latency and area efficient sequential circuit design. In the fulfillment of these objectives, the application of optimum design technology is essential. A counter comprises of the sequential circuit, having a broad variety of applications, including PLL, Digital to Analog, Signal Generators, Signal Synthesizers, etc. In this study a 4-bit Johnson counter is proposed for low power, high speed and cost efficient. The flip flop circuit utilized 14 transistors to produce a master D flip flop operation that triggered negative edge. The proposed counter is similar to the conventional counter's performance and price. With 43.22 percent less power dissipation than conventional versions, the suggested design has been found 48.86 percent faster. In the proposed counter, the transistor requirements are also 69.5 percent reduced, giving them an optimal area design.

MODERN IMPLEMENTATION OF JOHNSON COUNTER IN LOW POWER DIGITAL LOGICS USING CLOCK TIMING TECHNIQUES

The instinctive purpose of this study is to make VLSI circuits as low power consuming as possible. A lot of work has been done to reduce the operational power dissipation of the circuit, and reducing the power of sequential circuits is most important as it has clock as one of its input. Johnson counters are the sequential circuits which have so many unwanted switching of the clock pulses. Clock gating is the technique which reduces the power dissipation by eliminating the unwanted switching of the clock pulses. In this technique, the clock is supplied when output is different from the input and the clock is suppressed when output is same as the input. A new design of Johnson counter was studied in which additional circuitry of clock gating was used the unnecessary switching of the clock pulses and thus, to improve the power dissipation. It reduced the power to appreciable amount but this logic increased the chip area increasing the number of transistors. In this design, the optimization can be done in various blocks. Flip-flop being used in master slave mode consume huge power and the logic gates are also the site of power dissipation. So, a new design is proposed which comprises of proposed flip-flop design and modified logic gates design and a proposed design is simulated with the help of HSPICE which gives huge power reduction.

ANALYSIS OF DATA SKIPPING USING LOW TRANSITION SWITCH REGISTERS

The emerging scenario in the fields of VLSI testing has its own demand for fault diagnosis in VLSI circuits. If the area and size of the circuit increases the problem of test generation time becoming very tough. Efficient techniques for test generations are essential in order to reduce the test generation time and size. In Existing methods, Low transition Switch Register (LTSR) applies the corresponding repeated patterns of the generated test data. The complication in the LTSR technique exponentially increases power with respect to the circuit size. In case of circuit which has more stuck-at-fault, the LTSR method fails to provide suitable fault coverage and low power consumption. The proposed test data skipping scheme using Reconfigurable Johnson counter reduces the test data volume from the multiple test pattern and reduces switching transitions by skipping the test sequence mostly between the consecutive test sequences. The RJC based Test data skipping scheme has additional circuit which consists of various counters, Bit skipping circuit and logic gates. Memory unit consists of the whole test sequence then these test sequences are fed to RJC and Switching Transition counter. The consecutive test sequence are eliminated or skipped by comparing those counters and the state analysis of FSM. The proposed test data skipping scheme circuit is developed to achieve minimum test patterns and reduced scan power by skipping long scan chain switching activities. This present work with the above mentioned issues for LTSR and existing in VLSI circuits is to examine all detectable faults with proposed circuit. The Efficiency of such system is tested by Xilinx and ISE tools to generate test patterns to achieve high fault coverage with low power consumption over the conventional systems.

Fuzzy Logic Based Dryer Controller

The fuzzy logic control system determines the real-world constraint of the dryer’s heating rate to the dryer driver circuit which is constructed with the pulse width modulation (PWM) technique. Input and output operations to and from the computer system are carried out via parallel interfacing and Turbo C++ programming. The humidity sensing circuit is constructed around a 555 timer with astable operation which is a non-sinusoidal oscillator. This humidity sensing circuit produces a rectangular wave with the frequency indirectly proportional to the sensed humidity. In order to achieve the perfectively symmetrical square wave as well as to reduce the frequency value, the clocked flip-flop, CD4017BC that is divided by 10 Johnson counter with 10 decoded outputs and a carry out bit is added to the timer’s output. The resultant frequency is applied into the computer system integrating with the fuzzy logic and it determines the frequency value and its rate of change which are input to the fuzzy logic control system.

Design and Implementation of Low Power Ring and Johnson Counter using Transistor Resizing Technology by VHDL

Design and Implementation of Low Power Ring and Johnson Counter using Transistor Resizing Technology by VHDL

Low Power 130 nm CMOS Johnson Counter with Clock Gating Technique

In a very large scale integration (VLSI) of integrated circuit (IC) nowadays, digital circuit with low power design is the target of the IC designer. This is to prolong the battery life of the circuit especially if it is meant for wearable devices. In most of the digital circuits, counters are used widely and these counters consumed a lot of power. Therefore in this project the reduction of power consumption of Johnson Counter by using clock gating technique is presented. Johnson Counter is used extensively to generate particular data and shift the data synchronously as per the output sequence of the counter. To ensure the power consumption is reduced, a clock gating technique is incorporated to the Johnson Counter. This counter is implemented in Cadence software using 130 nm Complementary Metal Oxide Semiconductor (CMOS) technology. The design is observed by comparing the design of a 4 bit Johnson Counter using clock gating technique and another 4 bit Johnson Counter without using the clock gating technique. The result shows the power consumption of the Johnson Counter using the clock gating technique is 21.22 μW while the regular Johnson Counter consumed 67.09 μW. Thus the power consumption is reduced by about 68.3% when a clock gating technique is used.

Design of low power johnson counter using lector technique using 50nm technology

Design of low power johnson counter using lector technique using 50nm technology

Precision control of a sensorless PM BLDC motor using PLL control algorithm

This paper presents particular methods for deployment of precision control of a sensorless permanent magnet brushless DC (PM BLDC) motor using PLL control algorithm. Firstly, we utilizes the third harmonic of the motor internal voltages to determine the commutation instants of the PM BLDC motor for sensorless control. The waveform of the motor internal voltages (or back emf) contains fundamental and higher-order frequency harmonics. Therefore, the third harmonic component is extracted from the stator phase voltage. The resulting third harmonic signal maintains a constant phase relationship with the rotor flux at any motor speed and load condition. And is practically free of noise that can be introduced by the inverter switching, making this a robust sensing method. As a result, the method described here is not sensitive to filtering delays, allowing the motor to achieve a good performance over a wide speed range. For conventional 6-pulse control using the Hall-IC alone, this sensor misalignment would pose problems such as excessive torque ripple, noise, and inefficiency. Therefore, to implement the third harmonic sensing methods and speed control algorithm in this paper, the principle of the Johnson counter is used and it can estimate the same Hall-ICs signal with a non-difference phase resulting from the signals of the Johnson counter. Also, to precise control of a sensorless PM BLDC motor, we applied the position signal of phase lock loop (PLL) control algorithm and the remainder scheme in this paper, thus one can operate PM BLDC motor in high performance. Also, a simple starting method and speed estimation approach are proposed. Simulation an experimental results are provided, to demonstrate the validity of the precision control of a sensorless PM BLDC motor using PLL control algorithm.

Photonic processing of all‐optical Johnson counter using semiconductor optical amplifiers

This study presents a novel design of Johnson counter using D flip-flops. The performance of D flip-flop is carried out by exploiting the cross-gain modulation effect in semiconductor optical amplifier (SOA), purging the use of components like polarisation controllers, switches and so on. Performance is evaluated in terms of various variants like operational speed, cost effectiveness of design, rise time/fall time, quality of signal received and the system is found to give better results in terms of extinction ratio even without any feedback path. The Johnson counter or twisted ring counter is implemented using three all-optical D flip-flops producing six states. The D flip-flop incorporates travelling wave SOA and all-optical NOT gate. The proposed counter is reasonably valuable as it desires half of the flip-flops in association to other ring counters which directly reduce the cost of the system.

A ROM Driving Circuit for RFID Tags Based on a-IGZO TFTs

This paper proposes a read-only memory driving circuit for RFID tags based on a-IGZO thin-film transistors. The circuit consists of a Johnson counter and monotype complementary gates. By utilizing complementary signals to drive a decoder based on monotype complementary gates, the propagation delay can be decreased and the redundant current can be reduced. The Johnson counter reduces the number of registers. The new circuit can effectively avoid glitch generation, and reduce circuit power consumption and delay.

Computational design of synchronous sequential structures in biological systems

Numerous applications of synthetic biology require the implementation of scalable and robust biological circuits with information processing capabilities. Basic logic structures, such as logic gates, have already been implemented in prokaryotic as well as in eukaryotic cells. Biological memory structures have also been implemented either in vitro or in vivo. However, these implementations are still in their infancy compared to their electronic equivalents. Their response is mainly asynchronous. We may learn from electronic computer systems that robust and scalable computing devices can be implemented only with edge-triggered synchronous sequential structures. Implementation of such structures, however, has yet to be performed in the synthetic biological systems even on the conceptual level.Herein we describe the computational design and analysis of edge-triggered D flip-flop in master–slave configuration based on transcriptional logic. We assess the robustness of the proposed structure with its global sensitivity as well as parameter sweep analysis. Furthermore, we describe the design of a robust Johnson counter, which can count up to 2n cellular events using a sequence of n flip-flops. Changing the state of the counter is edge-triggered either with synchronization, i.e. clock signal, or with a pulse, which corresponds to the occurrence of observed event within the cellular environment. To the best of our knowledge this represents the design of the first biological synchronous sequential structure on such level of complexity.

Design and Analysis of 4 Bit Johnson Counter Using Clock Gating

In VLSI design the reduction of power is an important criterion. The performance of a system mainly depends on the method of designing of various blocks of that system. To provide an efficient and meaningful architecture of a VLSI chip, a devoted design is needed which is power serviceable with less intricate. As computer systems have sequential circuit mostly, hence it is very necessary to design a sequential circuit which is more efficient and less power consuming. As different kind of counters are the important segments for different sequential circuits. Here, in paper we have proposed an efficient clock gating 4-bit Johnson counter using low power d flip flop. Power of d-flip flop is reduced by using power gating technique. By doing analysis in cadence at 180nm technology it is counted that our proposed design has lower power consumption i.e. power of the proposed design comes to be reduced by 40.3% which is 62.63e-6 and the reduced output is 37.4e-6. This is a great achievement in the VLSI industry than the conventional design, with a little enhancement of delay.

DESIGN AND IMPLIMENTATION OF TEST PATTERN GENERATOR FOR DESIGN UNDER TEST

The patterns generated by LFSR for BIST as lack of correlation between the test vectors. Hence in order to improve the correlation of the test vector the patterns were generated using gray counter and decoder. In this paper we implement low power BIST for 4-bit multiplier. Main aspect of this is to implement low power BIST with increased fault coverage. This use the gray counter, decoder and accumulator as test pattern generator with changing the seed value for every 2 power m cycle, so for this purpose which use counter for monitoring the number of cycles. Hence the respective area optimization and power reduction can be achieved. Simulation outcome on multiplier circuit show a limiting of area and power than reconfigurable Johnson counter and LFSR. We implement the design using verilog HDL and Tool used for implementation is XILINX 13.2 and simulation is performed by using modelsim.

A low power 10-bit CMOS cyclic D/A converter with an improved Johnson counter and a capacitor swapping technique

A 10-bit CMOS cyclic D/A converter based on an improved Johnson counter and a capacitor swapping technique is described. In order to reduce the capacitor mismatching errors, we propose that two capacitors are alternately swapped depending on the input data. Further, a half differential architecture to reduce offset errors and an improved Johnson counter are also discussed. With a 0.35 µm Samsung CMOS technology, the measured SFDR is about 65 dB, when the input frequency is 1 MHz at a clock frequency of 2 MHz. The power consumption is only 240 µW at 3.3 V power supply. The measured INL and DNL are within ±0.7 and ±0.7 LSB, respectively.

LOW POWER TEST PATTERN GENERATION FOR BIST APPLICATIONS

This paper proposes a novel test pattern generator (TPG) for built-in self-test. Our method generates multiple single input change (MSIC) vectors in a pattern, i.e., each vector applied to a scan chain is an SIC vector. A reconfigurable Johnson counter and a scalable SIC counter are developed to generate a class of minimum transition sequences. The proposed TPG is flexible to both the test-per-clock and the test-per-scan schemes. A theory is also developed to represent and analyze the sequences and to extract a class of MSIC sequences. Analysis results show that the produced MSIC sequences have the favorable features of uniform distribution and low input transition density. Simulation results with ISCAS benchmarks demonstrate that MSIC can save test power and impose no more than 7.5% overhead for a scan design. It also achieves the target fault coverage without increasing the test length.