ANALYSIS OF DATA SKIPPING USING LOW TRANSITION SWITCH REGISTERS

Abstract

The emerging scenario in the fields of VLSI testing has its own demand for fault diagnosis in VLSI circuits. If the area and size of the circuit increases the problem of test generation time becoming very tough. Efficient techniques for test generations are essential in order to reduce the test generation time and size. In Existing methods, Low transition Switch Register (LTSR) applies the corresponding repeated patterns of the generated test data. The complication in the LTSR technique exponentially increases power with respect to the circuit size. In case of circuit which has more stuck-at-fault, the LTSR method fails to provide suitable fault coverage and low power consumption. The proposed test data skipping scheme using Reconfigurable Johnson counter reduces the test data volume from the multiple test pattern and reduces switching transitions by skipping the test sequence mostly between the consecutive test sequences. The RJC based Test data skipping scheme has additional circuit which consists of various counters, Bit skipping circuit and logic gates. Memory unit consists of the whole test sequence then these test sequences are fed to RJC and Switching Transition counter. The consecutive test sequence are eliminated or skipped by comparing those counters and the state analysis of FSM. The proposed test data skipping scheme circuit is developed to achieve minimum test patterns and reduced scan power by skipping long scan chain switching activities. This present work with the above mentioned issues for LTSR and existing in VLSI circuits is to examine all detectable faults with proposed circuit. The Efficiency of such system is tested by Xilinx and ISE tools to generate test patterns to achieve high fault coverage with low power consumption over the conventional systems.