DESIGN AND IMPLIMENTATION OF TEST PATTERN GENERATOR FOR DESIGN UNDER TEST

Abstract

The patterns generated by LFSR for BIST as lack of correlation between the test vectors. Hence in order to improve the correlation of the test vector the patterns were generated using gray counter and decoder. In this paper we implement low power BIST for 4-bit multiplier. Main aspect of this is to implement low power BIST with increased fault coverage. This use the gray counter, decoder and accumulator as test pattern generator with changing the seed value for every 2 power m cycle, so for this purpose which use counter for monitoring the number of cycles. Hence the respective area optimization and power reduction can be achieved. Simulation outcome on multiplier circuit show a limiting of area and power than reconfigurable Johnson counter and LFSR. We implement the design using verilog HDL and Tool used for implementation is XILINX 13.2 and simulation is performed by using modelsim.