Constant-Time Synchronous Binary Counter With Minimal Clock Period

Abstract

A synchronous binary counter is one of the basic components widely used in VLSI design, and it is required to be fast and support a wide bit-width in many applications. However, most of the previous counters are associated with a limited counting rate due to large fan-outs and long carry chains, especially when the counter size is not small. This brief proposes a new fast structure for synchronous binary counting, which has a minimal counting period for practical counter sizes ranging from 8 to 128 bits. We first adopt an 1-bit Johnson counter to reduce the overall hardware complexity, and then duplicate the 1-bit Johnson counter to decrease the propagation delay caused by large fan-outs. Implementation results show that the proposed design can be realized with a small number of flip-flops, which is almost linear to the counter size, and it operates at a clock frequency of 2GHz in a 65nm CMOS technology, being limited only by the counting rate of the least significant bit.