Analysis and optimal design of johnson counter

Abstract

The power consumption and propagation delay in a digital system is mainly due to sequential circuits. VLSI designers were primarily focused with low power, decreased latency and area efficient sequential circuit design. In the fulfillment of these objectives, the application of optimum design technology is essential. A counter comprises of the sequential circuit, having a broad variety of applications, including PLL, Digital to Analog, Signal Generators, Signal Synthesizers, etc. In this study a 4-bit Johnson counter is proposed for low power, high speed and cost efficient. The flip flop circuit utilized 14 transistors to produce a master D flip flop operation that triggered negative edge. The proposed counter is similar to the conventional counter's performance and price. With 43.22 percent less power dissipation than conventional versions, the suggested design has been found 48.86 percent faster. In the proposed counter, the transistor requirements are also 69.5 percent reduced, giving them an optimal area design.