Inversion Region Research Articles

Low-Leakage Double-Body MOSFET: A Promising Circuit-Level Technique for Deep-Submicron Analog Integrated Circuit Design

Since the leakage currents are dramatically increasing while the MOS transistors scale down to deep-submicron processes, the [Formula: see text]–[Formula: see text] characteristic of the channel is varied unintentionally. As a result, the analog integrated circuit (IC) designs based on it (at above 100-nm technologies) will malfunction. In this paper, a novel low-leakage double-body MOSFET (LLDB-M), as a circuit-level scheme in answering to the need for the current-mode analog IC design in deep-submicron processes, is proposed. In this technique, the sub-threshold and gate-oxide tunneling leakage currents (as two major parts) are reduced via lowering the gate-source voltage and increasing the threshold voltage of the MOS transistor. An LLDB-M consists of two typical transistors — the first one is the main transistor and the latter implements the shift-voltage to reduce the gate-source voltage and floor of the channel leakage currents. The drain, gate, and body of the main transistor as well as the body and source of the second one, organize the terminals of an LLDB-M. The proposed LLDB-M transistors are replaced with large-leakage transistors in a translinear loop in the weak inversion region and then the commonly-used circuits such-as the current mirror, one-quadrant multiplier-divider (at both up-down and stack topologies), the true RMS-DC converter, and the log-domain low-pass-filter are designed. The effectiveness and performance of the proposed LLDB-M technique and circuits are evaluated using HSPICE software in 22-nm BSIM4 CMOS process and Cadence Virtuoso tool in 65-nm TSMC CMOS technology. Post-layout simulation results show that the proposed circuit-level method by considerably reducing leakage currents could ensure the effective function of the current-mode analog IC designs in deep-submicron technologies. Also, comprehensive simulations have been performed to prove the robustness and reliability of the proposed circuits against process, voltage and temperature (PVT) changes.

Modelling and design of asynchronous receptive circuit for cone pathways

In this paper, asynchronous receptive circuit of retinal pathway is proposed for cone cells. Cone cells respond differently to different wavelengths of light and they are responsible for color vision. The cells present in retinal pathway namely cone photoreceptor, bipolar cell, amacrine cell and ganglion cell are mimicked using 180 nm Complementary Metal Oxide Semiconductor (CMOS) technology in strong inversion region. The proposed circuit is event based and hence asynchronous in nature. Additionally, amacrine stage is mimicked such that analog multiplexing occurs which is matching with its biological behavior. Both these features give output near to response of actual biological retinal pathway. The circuit detects wavelengths in visible spectrum of light with temporal contrast. At amacrine stage, selectivity is achieved without any external control signal which shows intelligent behavior at analog circuit level. The concept of color sensitivity of cone is considered to generate input stimulus of the circuit using Commission on Illumination (CIE) standard. The power consumed by the entire pathway circuit is 183 mW.

Low Mutation Load in a Supergene Underpinning Alternative Male Mating Strategies in Ruff (Calidris pugnax).

A paradox in evolutionary biology is how supergenes can maintain high fitness despite reduced effective population size, the suppression of recombination, and the expected accumulation of mutational load. The ruff supergene involves 2 rare inversion haplotypes (satellite and faeder). These are recessive lethals but with dominant effects on male mating strategies, plumage, and body size. Sequence divergence to the wild-type (independent) haplotype indicates that the inversion could be as old as 4 million years. Here, we have constructed a highly contiguous genome assembly of the inversion region for both the independent and satellite haplotypes. Based on the new data, we estimate that the recombination event(s) creating the satellite haplotype occurred only about 70,000 yr ago. Contrary to expectations for supergenes, we find no substantial expansion of repeats and only a modest mutation load on the satellite and faeder haplotypes despite high sequence divergence to the non-inverted haplotype (1.46%). The essential centromere protein N (CENPN) gene is disrupted by the inversion and is as well conserved on the inversion haplotypes as on the noninversion haplotype. These results suggest that the inversion may be much younger than previously thought. The low mutation load, despite recessive lethality, may be explained by the introgression of the inversion from a now extinct lineage.

Investigation of the Connection Schemes between Decks in 3D NAND Flash.

Dual-deck stacking technology is an effective solution for solving the contradiction between the demand for increasing storage layers and the challenge of the deep hole etching process in 3D NAND flash. The connection scheme between decks is a key technology for the dual-deck structure. It has become one of the necessary techniques for 3D NAND flash storage density improvement. This article mainly studies the impact of connection schemes between decks on cell reliability. Based on experimental data and simulation analysis, unfavorable effects were found as the gate channeling the breakdown and data retention characteristics of the top cells in the lower deck deteriorated due to the local electric field enhancement in the connection scheme without a poly-plug. This mainly contributed to the structural change of these cells within process impact. They will suffer secondary etching during the upper deck channel etching process due to alignment issues between the upper and lower decks. In another scheme with a poly-plug connection between decks, the saturation current of the channel decreased and the current variation increased. The fundamental cause of the current anomaly is that the Poly-plug has a certain shielding effect on channel inversion and the weak inversion region becomes a bottleneck for the channel current. The increase in variation is due to the shielding effect differences in the different structures of the poly-plug. Therefore, for the connection scheme without a poly-plug, the article proposes to improve device reliability by increasing the oxide thickness between decks and setting the top cells of the lower decks to be virtual cells. For the connection scheme with a poly-plug, the plug's N-type doping scheme is proposed to avoid the current dropping anomaly.

A Subthreshold Biased CMOS Ring Oscillator Model Design in 180-nm Process

In this paper, a 180-nm CMOS ring oscillator design, made with halo-implanted transistors and operating in the weak inversion region, is proposed, based on an undergraduate integrated circuit design course methodology for building logic gates and comparing simulated results with reviewed literature data. Halo-implanted channel transistors have a steeper and less distorted voltage characteristic curve compared to uniformly doped channel ones, which makes them a more appropriate option when designing asynchronous digital integrated circuits aimed at low bias and low power. Three gate models were created using weak inversion and pull-up and pull-down networks made with halo-implanted transistors. The results of the study and simulation of the three inverter digital gate topologies showed that the NOT inverter model, as expected, had a higher frequency than the NAND and NOR inverter models. The ring oscillators made with the NOT inverter came up with an 8.25-MHz switching frequency as well as a dynamic power close to 270 nW. A comparison with other ring oscillators from previous studies is also shown.

Thermodynamic properties of {glycerol (1) + tert-butanol (2)} mixtures at temperatures from 278 K to 323 K and pressures up to 100 MPa

In the present study the densities at atmospheric pressure and the compression coefficients of a binary liquid mixture {glycerol (1) + tert-butanol (2)} were measured within the temperature range from 278.15 K to 323.15 K (278.15, 288.15, 288.15, 308.15 and 323.15) and pressures up to 100 MPa (10, 25, 50, 75 and 100). Due to the limited solubility of tert-butanol in glycerol and the transition of the mixture to the solid phase the measurements at 278.15 K and 100 MPa were carried out up tox2 = 0.45 (x2 is the mole fraction of tert–butanol). The excess molar volumes, molar isothermal compression, molar isobaric thermal expansion, isochoric coefficient of thermal pressure mixtures, as well as the partial molar volumes of the mixture components, including their limit values, were calculated. The excess molar volume values at 323.15 K (the only temperature at which the compression was measured over the entire composition range) were found to be negative. The partial molar volume of glycerol (GL) at 323.15 K was characterized by the presence of a baric inversion region. The limiting partial molar volume of GL was shown to decrease in its own environment as the pressure rose and to increase in the TBA environment. The molar isothermal compression of the mixture varied depending on the composition without extremes, and the partial molar isothermal compression of GL had negative values. The molar isobaric thermal expansion of the mixture in the area of small tert-butanol (TBA) additives changed slightly at low temperatures and pressures and the increase in both the pressure and the temperature led to dispersion of their concentration dependences. The isochoric coefficient of thermal pressure decreased with an increase in x2, forming a small plateau at small TBA additions. The results obtained were discussed from the perspective of solute–solvent and solute–solute interactions.

Chromosomal inversion polymorphisms shape human brain morphology

The impact of chromosomal inversions on human brain morphology remains underexplored. We studied 35 common inversions classified from genotypes of 33,018 adults with European ancestry. The inversions at 2p22.3, 16p11.2, and 17q21.31 reach genome-wide significance, followed by 8p23.1 and 6p21.33, in their association with cortical and subcortical morphology. The 17q21.31, 8p23.1, and 16p11.2 regions comprise the LRRC37, OR7E, and NPIP duplicated gene families. We find the 17q21.31 MAPT inversion region, known for harboring neurological risk, to be the most salient locus among common variants for shaping and patterning the cortex. Overall, we observe the inverted orientations decreasing brain size, with the exception that the 2p22.3 inversion is associated with increased subcortical volume and the 8p23.1 inversion is associated with increased motor cortex. These significant inversions are in the genomic hotspots of neuropsychiatric loci. Our findings are generalizable to 3,472 children and demonstrate inversions as essential genetic variation to understand human brain phenotypes.

SiC MOSFETs Biased C-V Curves: A Temperature Investigation

In this paper, SiC MOSFETs capacitance is monitored when a DC bias is applied between Drain and Source. The arising capacitance exhibits a sharp peak in the inversion region which is related to the SiC/SiO2 interface traps properties. Temperature effects on such peak are investigated using both experimental and numerical results. The peak shifts toward lower Gate voltage as temperature increases, in agreement with the threshold voltage reduction at higher temperature.

Oxide and Interface Defect Analysis of lateral 4H-SiC MOSFETs through CV Characterization and TCAD Simulations

We investigated oxide and interface defects of lateral 4H-SiC MOSFETs through capacitance-voltage (C-V) and conductance-voltage (G-V) characterization at various frequencies and temperatures. By employing consecutive up and down sweeps of the gate voltage at three different temperatures, we experimentally characterized the hysteresis width as the difference between up and down sweeps in the depletion to accumulation (d-a) and depletion to inversion (d-i) regions. We observed an increase in the hysteresis width with decreasing temperature. Although the hysteresis width is not affected by the small-signal frequency, at the same time, increasing the frequency leads to a strong stretch-out effect, especially in the d-i region.Our measurement results indicate that the hysteresis deformation of the C-V curves is dominated by three different trap types. First, interface acceptor-like defects located close to the conduction band can follow the small-signal frequency. Slower acceptor-like border traps with trap levels both close to the conduction band and in the middle of the band gap are however responsible for the increase of trapped negative charge with increasing gate voltage. Finally, we assume the presence of a fixed positive charge.

Influence of Outer Oxide Charges on the Electrostatics of Metal-Insulator-Semiconductor Tunnel Diode

In this work, the impact of outer oxide charges on the electrostatics of metal-insulator-semiconductor tunnel diodes (MISTD) is discussed. The existence of outer oxide charges will significantly affect the critical voltage V c of MISTD in the strong inversion region. At the bias voltage of V < V c, the MISTD works like a traditional metal-oxide-semiconductor (MOS) capacitor. However, at the bias voltage of V > V c, the MISTD goes to deep depletion. V c is an important boundary for the electrostatics behavior of MISTD. We propose a model, considering the existing outer oxide charges, to calculate V c and compare the calculated results with V c extracted from our devices. V c of our devices is extracted by measuring high-frequency capacitance-voltage (HFCV) at 300 kHz. It is found that the model is able to fit well with the experimental results when the amount of outer oxide charges is in the magnitude of 2.5×1011 cm-2 for our devices. The model is fundamental but helpful for analyzing and designing a MISTD.

Optimization of Channel Structures in InP HEMT Technology for Cryogenic Low-Noise and Low-Power Operation

We report the impact from channel composition on the cryogenic low-noise performance at low dc power for a 100-nm gate-length InGaAs-InAlAs-InP high-electron mobility transistor (HEMT). Two indium (In) channel compositions, 65% and 80%, were studied by dc and RF characterization at 300 and 5 K. For the cryogenic low-noise optimization, it was important to increase the transconductance to gate–source capacitance ratio in the weak inversion region implying that a higher maximum cutoff frequency in the HEMT does not guarantee lower noise. The HEMT noise performance was obtained from noise measurements in a hybrid three-stage 4–8-GHz ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{C}$</tex-math> </inline-formula> -band) low-noise amplifier (LNA) down to 300- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu$</tex-math> </inline-formula> W dc power dissipation. While the HEMT LNA noise performance for both the channel compositions at 300 K was found to be comparable, the HEMT LNA at 5 K with 65% In channel showed a minimum noise temperature of 1.4 K, whereas the noise temperature in the HEMT LNA with 80% In channel HEMTs increased to 2.4 K. The difference in the noise became more pronounced at reduced dc power dissipation. The ultralow dc power of 300 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu$</tex-math> </inline-formula> W demonstrated for a cryogenic <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{C}$</tex-math> </inline-formula> -band LNA with an average noise temperature of 2.9 K and 24-dB gain is of interest for future qubit read-out electronics at 4 K.

Performance analysis of metal gate engineered junctionless nanosheet fet with a ft/fmax of 224/342ghz for beyond 5g (b5g) applications

This manuscript for the first time investigates the effect of Dual Metal on Gate Junctionless Nanosheet FET (DMG-JL-NSFET) for analog/RF applications. The entire analysis is performed for gate length (Lg) = 16 nm at 10μA/μm to focus the weak/moderate inversion region of operation. The results show a whooping amount of reduction in terms of output conductance (gds) (∼88.8%) due to the screening effect thereby enhancing the intrinsic gain (AV) (∼28.97%) of the DMG-JL-NSFET as compared to SMG-JL-NSFET. It is also found that the cut-off frequency (fT) and maximum oscillation frequency (fMAX) are increased by an amount of ∼11.82% and ∼2.91% respectively for DMG-JL-NSFET. Furthermore, it is elucidated that increasing the metal gate work function work difference (ΔW = φms-φmd) reduces the analog/RF performance of the DMG-JL-NSFET. The analysis revealed that increasing the ΔW from 0.3eV to 0.7eV deteriorates AV, fT, fMAX by an amount of ∼17.35%, ∼19.21%, and ∼37.57% respectively. Moreover, the implementation of HfO2 as high-k gate dielectric as a replacement for SiO2 degrades the analog/RF efficiency of DMG-JL-NSFET. Moreover, the DMG-JL-NSFET has provided a greater fT (∼224 GHz)/fMAX (∼342 GHz) indicating a promising candidature for future beyond 5G (B5G) applications.

Entropy Generation, Heat Transfer of Water Near Density Inversion Region with Relative Positions of Hot and Cold Walls: Numerical Analysis

This study investigates the entropy generation and heat transfer of water density inversion region in a square cavity with the different relative positions of hot and cold walls by numerical simulation. Mathematical models are solved using the EES (Engineering Equation Solver) program. A physical model is a 38 mm square cavity filled with water, with cold and hot wall temperatures maintained at 0oC and 10oC. Results indicated that the Nusselt number of cases 1 (cold and hot walls on both sides) is higher than case 2 (hot wall above, cold wall below) and case 3 (cold wall above, hot wall below) by 1.582 and 1.059 times, respectively. The average total generation per unit volume in case 1 increases by 1.577 times and 1.059 times, respectively, compared to cases 2 and 3, which almost correspondingly increase with heat transfer capacity. Entropy generation by fluid friction is negligible

Particle conserving approach to ac-dc driven interacting quantum dots with superconducting leads

The combined action of a dc bias and a microwave drive on the transport characteristic of a superconductor-quantum dot-superconductor junction is investigated. To cope with time dependent nonequilibrium effects and interactions in the quantum dot, we develop a general formalism for the dynamics of the density operator based on a particle conserving approach to superconductivity. Without invoking a broken U(1) symmetry, we identify a dynamical phase connected to the coherent transfer of Cooper pairs across the junction. In the weak-coupling limit, we show that besides quasiparticle transport, proximity induced superconducting correlations manifest in anomalous pair tunneling involving the transfer of a Cooper pair. The resulting generalized master equation in presence of the microwave drive showcases the characteristic bichromatic response due to the combination of the ac Josephson effect and an ac voltage. Analytical expressions for all harmonics in the driving frequency of both the current and the reduced dot operator are given for arbitrary driving strength. For the net dc current, the resulting photon assisted processes give rise to rich current-voltage characteristics. In addition to photon assisted subgap transport, we find regions of total current inversion in the stability diagram. There, the junction acts as a pump with the net dc current flowing against the applied dc bias. The first harmonic of the current, being closely related to the nonlinear dynamic susceptibility of the junction, is discussed at finite applied dc bias.

Implementation and performance analysis of QPSK system using pocket double gate asymmetric JLTFET for satellite communications

This work is intended to design a quadrature phase shift keying (QPSK) system starting from the device design, characterization and optimization which is then followed by the circuit level implementation and finally the system level configuration. Tunnel Field Effect Transistor (TFET) technology came into existence because of the inability of CMOS (Complementary Metal Oxide Semiconductor) to produce reduced leakage current (Ioff) in the subthreshold regime. With the effects of scaling and requirement of high doping concentrations, TFET is not capable to produce stable reduction in Ioff due to the variation in ON and OFF current. To improve the switching ratio of the current and to obtain good subthreshold swing (SS) by overcoming the limitations of junction TFET, a new device design is proposed for the first time in this work. A pocket double gate asymmetric Junction less TFET (poc-DG-AJLTFET) structure has been proposed in which uniform doping is used to eliminate the junctions and a pocket of length 2 nm made of Silicon–Germanium (SiGe) material has been introduced to improve the designed structure performance in the weak inversion region and increase the drive current (ION). The work function has been tuned to produce the best results for poc-DG-AJLTFET and with our proposed poc-DG-AJLTFET, effects of interface traps are eliminated as against conventional JLTFET structures. The notion that low-threshold voltage device yields high IOFF has been proved wrong with our poc-DG-AJLTFET design, as it produced low threshold voltage with lower IOFF which reduced the power dissipation. Numerical results show that drain induced barrier lowering (DIBL) of 2.75 mV/V is achieved which could be less than 35 times required for short channel effects to be minimum. In terms of gate to drain capacitance (Cgd), it is found that ~ 103 reduction which greatly improves device inertia to internal electrical interference. Also, improvement in transconductance is achieved by 104 times, 103 times improvement in ION/IOFF ratio, and 400 times higher unity gain cutoff-frequency (ft) which would be required by all communication systems. The Verilog models of the designed device are used to construct the leaf cells of quadrature phase shift keying (QPSK) system and the implemented QPSK system is taken as a key evaluator in the performance evaluation in terms of propagation delay and power consumption of poc-DG-AJLTFET in modern satellite communication systems.

The rate of chromosomal inversion fixation in plant genomes is highly variable.

Chromosomal inversions are theorized to play an important role in adaptation by preventing recombination, but testing this hypothesis requires an understanding of the rate of inversion fixation. Here, we use chromosome-level whole-genome assemblies for 32 genera of plants to ask how fast inversions accumulate and what factors affect this rate. We find that on average species accumulate 4-25 inversions per million generations, but this rate is highly variable, and we find no correlation between sequence divergence or repeat content and the number of inversions or the proportion of genome that was inverted and only a small correlation with chromosome size. We also find that inversion regions are depleted for genes and enriched for TEs compared to the genomic background. This suggests that idiosyncratic forces, like natural selection and demography, are controlling how fast inversions fix.

Electrical deterioration of 4H-SiC MOS capacitors due to bulk and interface traps induced by proton irradiation

In this study, the displacement damage dose (DDD) effects of proton irradiation on bulk crystal and interfacial properties of 4H-SiC MOS capacitors (MOSCs) were investigated. The Monte Carlo calculation code named SRIM (Stopping and Range of Ions in Matter) was first used to predict the depth profiles and damage distributions of protons. The 4H-SiC MOSCs were irradiated with 60, 100, 150 keV protons to fluences ranging from 5 × 1011 to 5 × 1013 cm−2. Capacitance-voltage (C-V) curves of the MOSCs were then measured to characterize the variation of the electrically active defects in 4H-SiC MOSCs. The results revealed that the non-ionization energy loss of incident protons leads to the accumulation of the primary defects in bulk SiC crystal as well as the increase of the interface traps between SiO2 and SiC crystal. A distinctive bump phenomenon was found in the weak inversion region of the C-V curve and it became more prominent with the increase of proton fluence, providing evidence for the existence of bulk traps. Furthermore, the incident proton energy is also a crucial factor in interface deterioration, suggesting that more interface traps would be formed when the proton damage peak is closer to the SiO2/SiC interface.

On the current conduction mechanisms of WO3/n-Ge Schottky interfaces

Electrical properties of n-Ge contacts tailored with nanostructured WO3 is analysed using current–voltage (I-V) and capacitive-voltage (C-V) measurements. Au/WO3/n-Ge heterostructure show its significant improvement in terms of high forward current and high magnitude of rectification ratio (RR = 3040 at ± 0.5V) than compared to contact without interlayer. The series resistance evaluated using Cheung’s method found to be very low (Rs = 17 Ω) in contacts with WO3 interlayer than compared to pristine sample. The influence of WO3 interfacial layer in defining the accumulation and inversion regions is clearly observed in the C-V characteristics measured at 1 MHz. A transition from ohmic conduction at low bias voltages to trap charge limited current (TCLC) conduction at high bias voltages is observed in the case of Au/WO3/n-Ge contacts. The distribution of traps or defects at the oxide-Ge interface possibly associated to the observed current conduction mechanisms at high bias regions. Very low series resistance, high rectification ratio and high forward currents of Au/WO3/n-Ge contacts show its applicability in optoelectronic and photovoltaic applications.

High-low Kelvin probe force spectroscopy for measuring the interface state density.

The recently proposed high-low Kelvin probe force microscopy (KPFM) enables evaluation of the effects of semiconductor interface states with high spatial resolution using high and low AC bias frequencies compared with the cutoff frequency of the carrier transfer between the interface and bulk states. Information on the energy spectrum of the interface state density is important for actual semiconductor device evaluation, and there is a need to develop a method for obtaining such physical quantities. Here, we propose high-low Kelvin probe force spectroscopy (high-low KPFS), an electrostatic force spectroscopy method using high- and low-frequency AC bias voltages to measure the interface state density inside semiconductors. We derive an analytical expression for the electrostatic forces between a tip and a semiconductor sample in the accumulation, depletion, and inversion regions, taking into account the charge transfer between the bulk and interface states in semiconductors. We show that the analysis of electrostatic forces in the depletion region at high- and low-frequency AC bias voltages provides information about the interface state density in the semiconductor bandgap. As a preliminary experiment, high-low KPFS measurements were performed on ion-implanted silicon surfaces to confirm the dependence of the electrostatic force on the frequency of the AC bias voltage and obtain the interface state density.

Discovery, structure and function of plasmid mediated shufflon

Antimicrobial resistance has become a major public health issue of global concern. Conjugation is an important way for fast spreading drug-resistant plasmids, during which the type Ⅳ pili plays an important role. Type Ⅳ pili can adhere on the surfaces of host cell and other medium, facilitating formation of bacterial biofilms, bacterial aggregations and microcolonies, and is also a critical factor in liquid conjugation. PilV is an adhesin-type protein found on the tip of type Ⅳ pili encoded by plasmid R64, and can recognize the lipopolysaccharid (LPS) molecules that locate on bacterial membrane. The shufflon is a clustered inversion region that diversifies the PilV protein, which consequently affects the recipient recognition and conjugation frequency in liquid mating. The shufflon was firstly discovered on an IncI1 plasmid R64 and has been identified subsequently in plasmids IncI2, IncK and IncZ, as well as the pathogenicity island of Salmonella typhi. The shufflon consists of four segments including A, B, C, and D, and a specific recombination site named sfx. The shufflon is regulated by its downstream-located recombinase-encoding gene rci, and different rearrangements of the shufflon region in different plasmids were observed. Mobile colistin resistance gene mcr-1, which has attracted substantial attentions recently, is mainly located in IncI2 plasmid. The shufflon may be one of the contributors to fast spread of mcr-1. Herein, we reviewed the discovery, structure, function and prevalence of plasmid mediated shufflon, aiming to provide a theoretical basis on transmission mechanism and control strategy of drug-resistant plasmids.