Intrinsic Cutoff Frequency Research Articles

Transport and performance of a zero-Schottky barrier and doped contacts graphene nanoribbon transistors

The transport physics and performance of a top gate graphene nanoribbon (GNR) on an insulator transistor are studied for both the MOSFET like doped source–drain and the zero-Schottky barrier source–drain contacts. A voltage controlled tunnel barrier is the device transport physics. The doped source–drain contact device has a higher gate capacitance, higher transconductance, higher on/off current ratio and higher on-state current. The higher on-state current results in a lower switching delay of 17 fs, and the higher transconductance results in a higher intrinsic cut-off frequency of 27 THz in the doped source–drain contact device. The gate voltage, beyond the source–channel flat band condition, modulates both the tunnel and the thermal barrier in the doped source–drain contact devices and the tunnel barrier only in the Schottky contact devices. This limits the on-state current of Schottky contact devices.

Performance of $n$-Type InSb and InAs Nanowire Field-Effect Transistors

The electronic structure of highly scaled InSb and InAs nanowire (NW) field-effect transistors (FETs) is calculated with an eight-band kmiddotp model. Cross sections of 4 nm or less result in bandgaps of 0.8 eV or more. For these cross sections, all devices are single moded and operate in the quantum capacitance limit. Analytical expressions for the transconductance, cutoff frequency, and gate delay time are presented and compared to numerical results. The dependence of the intrinsic cutoff frequency on drive current is weak, scaling as radic{ <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ID</i> } with values in the 4-7 THz range that are good for RF applications. The gate delay times strongly depend on the drive current, scaling as I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3/2</sup> with values ranging from 25 to 132 fs which are competitive for digital applications.

A heterodyne method for the thermal observation of the electrical behavior of high-frequency integrated circuits

The observation of spectral components of the power dissipated by devices and circuits in integrated circuits (IC) by temperature measurements is limited by the bandwidth of either the temperature transducer or the intrinsic cut-off frequency provided by the thermal coupling inside the chip. In this paper, we use a heterodyne method to observe the high-frequency behavior of circuits and devices by means of low-frequency lock-in temperature measurements. As experimental results, two applications of the technique are presented: detection of hot spots in ICs activated by high-frequency electrical signals and the observation of the frequency response of an integrated resistor through temperature measurements. The heterodyne method has been used in this paper with four different measurement techniques: embedded differential BiCMOS temperature sensor, laser reflectometer, laser interferometer and internal IR laser deflection meter.

Microwave rectification by a carbon nanotube Schottky diode

Carbon nanotube Schottky diodes have been fabricated in an all-photolithographic process using dissimilar contact metals on high-frequency compatible substrates (quartz and sapphire). Diodes show near-ideal behavior and rectify currents of up to 100nA and at frequencies of up to 18GHz. The voltage and frequency dependence is used to estimate the junction capacitance of ∼10−18F and the intrinsic device cutoff frequency of ∼400GHz.

High Performance InAlAs/InAs/InGaAs Pseudomorphic High Electron Mobility Transistors

AbstractHigh electron mobility transistors (HEMTs) with a pseudomorphically strained InAs channel (InAs-PHEMTs) were fabricated, and their high frequency characteristics were estimated by measuring the S-parameters. For a VDS of 1.4 V and VGS of 0.3 V, InAs-PHEMTs showed an excellent intrinsic cut-off frequency (fT, int.) as high as 90 GHz regardless of their longer LG (0.7 μm). Since fT is known to be inversely proportional to LG to the first approximation, fT, int. of our InAs-PHEMTs may reach 630 GHz if their LG is reduced to 0.1 μm.Moreover, we calculated the InAs-PHEMTs' energy state and potential profile by self-consistently solving the Schrödinger and Poisson equations. In solving the Schrödinger equation, the energy-dependent effective mass was employed to take into account the strong non-parabolicity of InAs conduction-band based on the k·p perturbation theory by E. O. Kane. It was clarified that most electrons are confined to the InAs layer. On the contrary, if the non-parabolicity is not taken into account, electrons will spread over the InGaAs channel layer.

Ultrahigh Frequency Carbon Nanotube Transistor Based on a Single Nanotube

Single-walled carbon nanotube field-effect transistors (CNT FETs) are predicted to have intrinsic cutoff frequencies approaching the THz range. Here ldquointrinsicrdquo means that the parasitic capacitance due to fringing fields is negligible compared to the gate-source capacitance required to modulate the conductance. In practice, although there are strategies proposed to mitigate this based on parallel arrays of CNT FETs, this parasitic capacitance dominates most geometries (even aligned arrays to date). In this work we show nanotube transistor performance with maximum stable gain above 1 GHz (even including the parasitics) by combining ldquoon-chiprdquo the electrical properties of 100 CNT FETs fabricated on one long nanotube. This also solves the problem of impedance matching by boosting the on current to a large (mA) value, and at the same time allows one to extract properties of each individual CNT FET, since they are identical in electrical characteristics as they are made out of the same CNT. This strategy opens the door to applications of carbon nanotube devices in the RF and microwave frequency range, a technologically relevant portion of the spectrum for both wired and wireless electronics, that has been (until now) incompatible with nanotube device technology.

Intrinsic current gain cutoff frequency of 30GHz with carbon nanotube transistors

High frequency capabilities of carbon nanotube field-effect transistors (CNTFETs) are investigated. Structures with a large number of single-walled carbon nanotubes were fabricated using dielecrophoresis to increase the density of nanotubes in the device channel. The authors obtained an intrinsic current gain cutoff frequency of 30GHz establishing state-of-the-art high frequency (hf) potentialities of CNTFETs. The device also showed a maximum stable gain above 10dB at 20GHz. Finally, the parameters of an equivalent circuit model of multitube CNTFET at 20GHz are determined, which open the route to the modeling of nanotubes-based hf electronics.

Temperature Dependence of High Frequency and Noise Performance of Sb-Heterostructure Millimeter-Wave Detectors

The temperature dependence of the microwave and noise performance of zero-bias Sb-heterostructure backward diodes for millimeter-wave detection have been investigated experimentally. Both the junction capacitance and junction resistance were found to decrease with decreasing temperature, while the intrinsic cutoff frequency and sensitivity are observed to increase as the temperature is lowered. A simple physical model that captures these effects is described. The directly measured voltage sensitivity at 50 GHz for a 2times2 mum 2 device increased from 3650 V/W at room temperature to 7190 V/W at 4.2 K. The measured noise equivalent power (NEP) decreased from 4.2 to 0.2 pW/Hz1/2 as the temperature was lowered from 298 K to 4.2 K when driven from a 50- Omega source. Based on the measured RF sensitivity, S-parameters, and noise spectrum, a NEP of 0.3 pW/Hz1/2 is projected for room-temperature operation at zero bias using a conjugately matched RF source

Significance of Gate Underlap Architecture in FinFETs for Low-Voltage Analog/RF Applications

In the present work, we analyze the enormous potential of source/drain extension (SDE) region engineering in FinFETs for Ultra Low-Voltage analog/rf applications. We show that SDE region design can simultaneously improve two key analog figures of merit (FOM) - intrinsic dc gain (AVO) and cut-off frequency (fT) for 60 nm FinFETs operated at low drive current (Ids = 5 µA/µm). The results are analyzed in terms of spacer-to- gradient ratio, a new design parameter for devices with non- abrupt source/drain regions. The present work provides new opportunities for realizing future ultra low-voltage/low-power analog/rf design with nanoscale SDE engineered FinFETs.

Source/drain extension region engineering in nanoscale double gate SOI MOSFETs: Novel design methodology for low-voltage analog applications

The present paper proposes for the first time, a novel design methodology based on the optimization of source/drain extension (SDE) regions to significantly improve the trade-off between intrinsic voltage gain ( A VO) and cut-off frequency ( f T) in nanoscale double gate (DG) devices. Our results show that an optimally designed 25 nm gate length SDE region engineered DG MOSFET operating at drain current of 10 μA/μm, exhibits up to 65% improvement in intrinsic voltage gain and 85% in cut-off frequency over devices designed with abrupt SDE regions. The influence of spacer width, lateral source/drain doping gradient and symmetric as well as asymmetrically designed SDE regions on key analog figures of merit (FOM) such as transconductance ( g m), transconductance-to-current ratio ( g m/ I ds), Early voltage ( V EA), output conductance ( g ds) and gate capacitances are examined in detail. The present work provides new opportunities for realizing future low-voltage/low-power analog circuits with nanoscale SDE engineered DG MOSFETs.

Source/Drain Extension Region Engineering in FinFETs for Low-Voltage Analog Applications

In this letter, we propose a novel design methodology for engineering source/drain extension (SDE) regions to simultaneously improve intrinsic dc gain (A <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VO</sub> ) and cutoff frequency (f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T </sub> ) of 25-nm gate-length FinFETs operated at low drain-current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds</sub> =10 muA/mum). SDE region optimization in 25-nm FinFETs results in exceptionally high values of A <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VO</sub> (~45 dB) and f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> (~70 GHz), which is nearly 2.5 times greater when compared to devices designed with abrupt SDE regions. The influence of spacer width, lateral source/drain doping gradient, and the spacer-to-gradient ratio on key analog figures of merit is examined in detail. This letter provides new opportunities for realizing future low-voltage/low-power analog design with nanoscale SDE-engineered FinFETs

Design and Optimization of FinFETs for Ultra-Low-Voltage Analog Applications

In this paper, we analyze the enormous potential of engineering source/drain extension (SDE) regions in FinFETs for ultra-low-voltage (ULV) analog applications. SDE region design can simultaneously improve two key analog figures of merit (FOM)-intrinsic dc gain (A <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VO</sub> ) and cutoff frequency (f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) for 60 and 30 nm FinFETs operated at low drive current (J <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds</sub> = 5 muA/mum). The improved A <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VO</sub> and f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> are nearly twice compared to those of devices with abrupt SDE regions. The influence of the SDE region profile and its impact on analog FOM is extensively analyzed. Results show that SDE region optimization provides an additional degree of freedom apart from device parameters (fin width and aspect ratio) to design future nanoscale analog devices. The results are analyzed in terms of spacer-to-straggle ratio-a new design parameter for SDE engineered devices. This paper provides new opportunities for realizing future ULV/low-power analog design with FinFETs.

Transitive X‐Ray Spectrum and PeV Gamma‐Ray Cutoff in the M87 Jet: Electron “Pevatron”

We propose a modified version of the X-ray spectral index and an intrinsic cutoff frequency of inverse Compton radiation from the brightest knot of the M87 jet, in conjunction with an application of the new conceptions of injection and diffusive shock acceleration (DSA) of electrons in magnetized filamentary plasma to the specified source. The drop of the X-ray flux density in a transitive frequency region is associated with the interplay of ordinary synchrotron cooling and weaker magnetic fields concomitant with the smaller scale filaments that allow the electron injection, while the radio-optical synchrotron continuum is dominantly established by the major electrons that are quasi-secularly bound to larger filaments. With reference to, particularly, the updated external Compton model, we demonstrate that in the Klein-Nishina regime fading inverse Comptonization, the injected electrons can be stochastically energized up to a Lorentz factor as high as 5 × 1010 in the temporal competition with diffuse synchrotron cooling; this value is larger than that attainable for a simple DSA scenario based on the resonant scattering diffusion of the gyrating electrons bound to a supposed magnetic field homogeneously pervading the entire knot. The upper limits of the photon frequency boosted via conceivable inverse Compton processes are predicted to be of the common order of ~1030 Hz. The variability of the broadband spectrum is also discussed in comparison to the features of a blazar light curve. The present scenario of a peta-eV (PeV; 1015 eV) electron accelerator, the Pevatron, might provide some guidance for exploring untrod hard X-ray and gamma-ray bands in forthcoming observations.

Time-dependent quantum transport and nonquasistatic effects in carbon nanotube transistors

Nonquasistatic effects in ac characteristics of carbon nanotube field-effect transistors are examined by solving a full time-dependent, open-boundary Schrödinger equation. The nonquasistatic characteristics, such as the finite channel charging time, and the dependence of small signal transconductance and gate capacitance on the frequency, are explored. The validity of the widely used quasistatic approximation is examined. The results show that the quasistatic approximation overestimates the transconductance and gate capacitance at high frequencies, but gives a more accurate value for the intrinsic cutoff frequency over a wide range of bias conditions.

Effect of phonon scattering on intrinsic delay and cutoff frequency of carbon nanotube FETs

The effect of phonon scattering on the intrinsic delay and cutoff frequency of Schottky-barrier carbon nanotube (CNT) FETs (CNTFETs) is examined. Carriers are mostly scattered by optical and zone-boundary phonons beyond the beginning of the channel. It is shown that the scattering has a small direct effect on the dc on current of the CNTFET, but it results in a significant decrease of intrinsic cutoff frequency and increase of intrinsic delay.

Accurate extraction and analysis of intrinsic cutoff frequency of sub-0.1 µm MOSFETs

A new RF method based on the accurate extraction of the intrinsic transconductance and gate–source channel capacitance from measured S-parameters is proposed to determine the intrinsic cutoff frequency of sub-0.1 µm MOSFETs. Using the RF technique, the intrinsic cutoff frequency enhancement with the linear dependence on 1/Lpoly2 is observed in sub-0.1 µm bulk n-MOSFETs. It is also observed that the reduction of extrinsic charging time is the most important to increase the measured cutoff frequency in sub-0.1 µm CMOS devices.

Dielectric scaling of a zero-Schottky-barrier, 5nm gate, carbon nanotube transistor with source/drain underlaps

The effect of gate dielectric on coaxially gated, Schottky-barrier, carbon nanotube field-effect transistors with source and drain underlaps is investigated. For 2nm thick dielectrics, the substitution of SiO2 with ZrO2 has little effect on the on-current and the subthreshold slope. The principal effect is a change in the intrinsic and parasitic gate capacitances which affects the delay time, cut-off frequency, and Coulomb blockade of the ambipolar leakage current. Using a relatively low-K gate dielectric (as opposed to a high-K gate dielectric) increases the speed performance by reducing parasitic components of the gate capacitance. For a 50nm long, 1.5nm diameter, zero-Schottky-barrier carbon nanotube (CNT) with a 5nm gate and a 2nm SiO2 dielectric, we obtain a delay time of 31fs, a cutoff frequency of 8.9THz, an inverse subthreshold slope S=66mV∕dec, and an on-off current ratio of 8×105 with VDD=0.4V. Oxide thickness dependence of the on-off current ratio, inverse subthreshold slope, and intrinsic cut-off frequency is also investigated.

ANALYSIS OF BANDWIDTH AND NONLINEAR EFFECTS IN InGaAs-BASED BALLISTIC NANODEVICES FOR APPLICATIONS UP TO THz RANGE

Analysis of nonlinear effects in InAlAs/InGaAs -based channels and three-terminal ballistic junctions (TBJs) is performed for applications up to THz range. Results show that InGaAs -based channels designed for ballistic operation exhibit high intrinsic cut-off frequency (fT ~ 10 THz ). Nonlinear effects in TBJs, which result from device geometry and space charge distribution, show good qualitative agreement with published results.

Performance of 2 nm gate length carbon nanotube field-effect transistors with source∕drain underlaps

The performance of coaxially gated, zero-Schottky-barrier, carbon nanotube field-effect transistors is investigated for gate lengths down to 2 nm with source and drain underlaps. Such devices can have nearly ideal subthreshold slopes of ∼63mV∕dec and maximum on∕off current ratios of 2.2×106 assuming 0.0–0.4 volt swing. The leakage mechanism is a combination of both intra-band and inter-band tunneling. For a 30 nm long carbon nanotube (CNT) with a 2 nm gate, Cg=3.13aF, the intrinsic switching time, τs=CgVDD∕ION, is 370 fs, and the intrinsic cut-off frequency defined by fT=gm∕(2πCg) is 1.6 THz. The ambipolar leakage current is suppressed by Coulomb blockade. Calculations are performed using a π-bond model and a self-consistent solution of the nonequilibrium Green function equations and Poisson’s equation.

Submicron gate Si3N4/AlGaN/GaN-metal-insulator-semiconductor heterostructure field-effect transistors

We present the characteristics of a quarter-micron gate metal-insulator-semiconductor heterostructure field-effect transistor (MISHFET) with Si/sub 3/N/sub 4/ film as a gate insulator. A detailed comparison of the MISHFET and an identical geometry HFET shows them to have the same radio frequency (RF) power gain and cut-off frequency, while the MISHFET has much lower gate-leakage currents and higher RF powers at operating frequencies as high as 26 GHz. The MISHFET gate-leakage currents are well below 100 pA at gate bias values from -10 V to +8 V. At zero gate bias, the drain saturation current is about 0.9 A/mm and it increases to 1.2 A/mm at +8 V gate bias. The output RF power of around 6 W/mm at 40 drain bias was found to be frequency independent in the range of 2 to 26 GHz. This power is 3 dB higher than that from HFET of the same geometry. The intrinsic cutoff frequency is /spl sim/63 GHz for both the HFET and the MISHFET. This corresponds to an average effective electron velocity in the MISHFET channel of 9.9/spl times/10/sup 6/ cm/s. The knee voltage and current saturation mechanisms in submicron MISHFETs and heterostructure field-effect transistors (HFET) are also discussed.