Significance of Gate Underlap Architecture in FinFETs for Low-Voltage Analog/RF Applications

Abstract

In the present work, we analyze the enormous potential of source/drain extension (SDE) region engineering in FinFETs for Ultra Low-Voltage analog/rf applications. We show that SDE region design can simultaneously improve two key analog figures of merit (FOM) - intrinsic dc gain (AVO) and cut-off frequency (fT) for 60 nm FinFETs operated at low drive current (Ids = 5 µA/µm). The results are analyzed in terms of spacer-to- gradient ratio, a new design parameter for devices with non- abrupt source/drain regions. The present work provides new opportunities for realizing future ultra low-voltage/low-power analog/rf design with nanoscale SDE engineered FinFETs.