Internal Capacitance Research Articles

Pre-Energization Concept for Overhead Lines in MTDC Grids Using DCCB Internal Capacitor

The integration of overhead lines in future MTDC grids leads to a higher fault rate compared to cables. Most of the faults are considered to be non-permanent, so that the line can be reconnected after dielectric recovery. The auto-reclosing procedure in HVDC systems reveals new challenges since multiple restrikes are possible within a short period of time. This paper proposes an auxiliary circuit for DC Circuit Breakers (DCCB) which enables to use the DCCB internal capacitor for the line pre-energization. A comprehensive description of the switchgear operations during the pre-energization sequence is provided and the fault property identification method is defined. The method is validated by simulations in a MTDC grid and a sensitivity analysis is carried out using EMTP-RV.

Analysis of junction capacitance characteristics of trench gate IGBT

Trench gate field termination IGBT represents the latest structure of insulated gate bipolar transistor (IGBT). Because the internal current of IGBT includes the charging and discharging current of gate capacitance and internal junction capacitance during switching transient, the influence of junction capacitance should be considered. The conductive channel of trench gate structure is different from that of planar gate structure, and the analysis method of junction capacitance using planar gate structure will inevitably bring some deviation. Based on the characteristics of trench gate structure, this paper analyzes the different expressions of internal gate-drain junction capacitance in two cases according to whether the base depletion layer can be widened to cover the trench gate, and finally carries out simulation and experimental verification.

Dynamic Phasor Modeling and Analysis of Three-Phase DC/DC/AC MMCs for Hybrid AC/DC Grids

The first comprehensive three-phase state-space dynamic phasor model (DPM) for the emerging class of dc/dc/ac modular multilevel converters (MMCs) is presented that accounts for both dc/dc and dc/ac power transfer mechanisms. The phasor model is derived in the α β 0-frame and includes frequency components from dc to third harmonic, which is shown to yield a high degree of matching for both steady-state and transients when compared against switched and time-averaged models, the latter of which is also derived in this work. An analytical solution procedure is then proposed that takes advantage of the phasor model time-invariance to find the full state solution at any operating point including the requisite open-loop modulating signals. Several analyses are carried out for two different dc/dc/ac MMC case study designs to explore the utility and versatility of the proposed DPM and solution procedure. Results show the patterns of internal current stresses and capacitor voltage ripples for the arms can vary significantly and in a nonsymmetrical manner, which is in stark contrast to the traditional dc/ac MMC.

A high-precision time-to-digital converter applied to CDC

This paper presents a high-precision CMOS time-to-digital converter (TDC) applied to a capacitance-to-digital converter (CDC). The time-to-digital converter in the capacitance-to-digital converter is used to measure the time interval between the charging time of the capacitor under test and the charging time of the internal reference capacitor. The time resolution of the TDC directly determines the capacitance resolution of the CDC. In order to improve the measurement resolution of TDC, a TDC structure based on phase-locked loop (PLL) is proposed. This paper first gives a capacitance-to-digital converter scheme, and then introduces the time-to-digital converter used in the scheme. The frequency multiplication technology of the phase-locked loop optimizes the integral nonlinearity (INL) of the interpolator and greatly improves the interpolation of the interpolation ratio. The TDC was realized in a 0.13-μm CMOS process, and the measurable time interval is 21.14μs. When the external reference clock is 200MHz, the resolution is 40.3ps and only 31 delay units are needed.

A clamping type DC circuit breaker with short fault isolation time and low energy dissipation

The development of DC grids faces challenges from DC fault protection. The conventional DC circuit breaker (DCCB) employs metal-oxide varistor (MOV) to isolate the faulted line, in which the fault isolation process is coupled with the energy dissipation process. In this study, a clamping type DCCB (CTCB) uses internal capacitors to clamp the converter voltage is proposed. Thanks to the proposed configuration, fault isolation and energy dissipation are decoupled, resulting in a fast fault isolation and low energy dissipation compared to the conventional DCCB. The working principle of the proposed CTCB is presented and verified in a DC grid simulation model. A comparison is made with the traditional DCCB. The fault isolation time can be reduced by 34.5 %. The dissipated energy can be reduced by 17.4 %. The energy dissipation power can be reduced by 76.2 %. <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sup>

Adaptive Energy Estimation for Supercapacitor Based on a Real-Time Voltage State Observer in Electric Vehicle Applications

As an energy storage or power buffering device, supercapacitor (SC) has incomparable advantages in terms of charging-discharging efficiency, response speed, and durability. Generally, a simplified energy estimation method based on a constant or rated capacitance can be used to evaluate the state-of-energy (SoE) of SCs. However, using a constant capacitance to evaluate the SoE of SC is very imprecise. Indeed, the SC internal parameters would change in accordance with the operating current and voltage such that the actual capacitance is far from the rated capacitance. This letter presents: a variable first-order resistance-capacitance equivalent circuit for dynamic modeling of the SC; a real-time voltage state observer used to estimate the variable internal capacitance and resistances of the SC; three different energy estimation methods; and simulated and experimental validations of the adaptive energy estimation method based on a 3000 F SC in electric vehicle applications. By using the SoE based on an experiment calibration as a reference standard, the proposed adaptive energy estimation method can improve over 0.75% of the estimated SoE error for the SC compared with the conventional estimation method.

Dynamic Simulation of a-IGZO TFT Circuits Using the Analytical Full Capacitance Model (AFCM)

The Analytical Full Capacitance Model (AFCM) for amorphous oxide semiconductors thin film transistors (AOSTFTs) is first validated, using a 19-stages Ring Oscillator (RO) fabricated and measured. The model was described in Verilog-A language to use it in a circuit simulator in this case SmartSpice from Silvaco. The model includes the extrinsic effects related to specific overlap capacitances present in bottom-gate AOSTFT structures. The dynamic behavior of the simulated circuit, when the TFT internal capacitances are increased or decreased and for different supply voltages of 10, 15 and 20 V, is compared with measured characteristics, obtaining a very good agreement. Afterwards, the AFCM is used to simulate the dynamic behavior of a pixel control circuit for a light emitting diode active matrix display (AMOLED), using an AOSTFT.

Impact of surface conditions changes on changes in thermodynamic properties of quasi 2D crystals

In continuation of our research regarding the phonon-induced properties of the low dimensional structures, we are investigating the impact of changes in boundary parameters onto the thermodynamic properties of the quasi 2D crystals (ultrathin films). Internal energy and thermal capacitance of the ultrathin film are theoretically analyzed and numerically and graphically presented for the various combinations of boundary surface parameters. This research is motivated by efforts to explain many unusual thermal properties of novel two-dimensional materials. The obtained results are also of great significance for the heat removal and other important physical properties and processes in ultrathin films, with special emphasis to the improvement of the superconducting properties towards the high TC superconductivity.

Fast Response Organic Supramolecular Transistors Utilizing In-Situ π-Ion Gels.

Despite their remarkable charge carrier mobility when forming well-ordered fibers, supramolecular transistors often suffer from poor processability that hinders device integration, resulting in disappointing transconductance and output currents. Here, a new class of supramolecular transistors, π-ion gel transistors (PIGTs), is presented. An in situ π-ion gel, which is an unprecedented composite of semiconducting nanofibers and an enclosed ionic liquid, is directly employed as an active material and internal capacitor. In comparison to other supramolecular transistors, a PIGT displays a high transconductance (133 µS) and output current (139 µA at -6 V), while retaining a high charge-carrier mobility (4.2 × 10-2 cm2 V-1 s-1 ) and on/off ratio (3.7 × 104 ). Importantly, the unique device configuration and the high ionic conductivity associated with the distinct nanosegregation enables the fastest response among accumulation-mode electrochemical-based transistors (<20 µs). Considering the advantages of the absence of dielectric layers and the facile fabrication process, PIGT has great potential to be utilized in printed flexible devices. The device platform is widely applicable to various supramolecular assemblies, shedding light on the interdisciplinary research of supramolecular chemistry and organic electronics.

Bidirectional single-loop current sensorless control applied to NPC multi-level converter considering conduction losses

The current feedback is considered as unavoidable part of most control system driving power electronic converters. However, it is possible to eliminate the use of current sensor, if properly calculated volt-second balance is applied to input inductor. This paper describes the implementation of current sensorless control technique applied to neutral point clamped multi-level converter, where only voltage control-loop is used to stabilize internal capacitors voltage, while inductor’s current is shaped by means of current sensorless control block in both discontinuous and continuous current modes. The capacitor voltage balancing is implemented by means of delta-controller that selects alternative capacitor in respect to main switching scheme. Finally, the analytical study of proposed solution is verified with simulation results.

A Method to Optimize 3D Microbatteries

The rapid development of information technology (IT) since the end of the 20th century and the technological progress of sensors and devices have familiarized the concept of the Internet of Things (IoT). So far, the miniaturization of the sensors and devices has significantly contributed to the rapid growth of the IoT ecosystem. However, compared with such technological progress on the sensors and devices, the miniaturization technology of the power sources for the off-grid operation of the electronics has not been well established, which hinders further prevalence of the IoT. Especially, for the integration with microelectronics, the high areal energy density is recognized as one of the key properties for such power sources.As one of the promising candidates for such IoT-enabled power sources, lithium-ion microbatteries have attracted attention. Especially, the three-dimensional design of the microbattery at full cell level has been investigated in order to improve the areal energy density while maintaining high power density. The benefit of the geometrical modification is the lowering of the internal resistance due to the reduction of the ion transport distance without reducing the battery capacity. Indeed, the recent advancement of a variety of 3D manufacturing technologies has allowed the realization of the 3D microbattery. However, the 3D electrode structure is limited to simple shapes such as interdigitated plate or cylindrical electrodes and, therefore, the battery performance is restricted by such electrode shapes. To design the 3D battery architecture beyond the interdigitated configuration, the 3D battery optimization method at the full cell level is vital. Also, the 3D battery optimization method is crucial from the point of view of industrial demand since there are a variety of IoT devices that have different functions, and it is demanding to optimize the battery following the requirements of each IoT device by hand. However, there are no reports regarding the 3D battery optimization methods at the full cell level.In this talk, we propose a novel battery optimization system at the full cell level, which consists of an automatic geometry generator and performance simulators. The geometry generator designs the full cell based on the random sampling by only receiving the size and the resolution of the 3D battery cell as the input data. For compatibility with the geometry generator, as one of the performance simulators, we newly propose the transmission line model, the so-called 3D porous electrode model, to compute the internal resistance of the 3D battery quickly. To demonstrate the effectiveness of our approach, the tradeoff frontier for the internal resistance and capacitance is created by plotting 200,000 data points as shown in Fig. 1 (a). From the figure, we successfully find new battery geometry (Geometry D in Fig. 1 (b)), which has both higher power and energy densities than the interdigitated plate configuration (Geometry C in Fig. 1 (b)). Figure 1

Active matching circuit to enhance the generated power of triboelectric nanogenerators

Converting mechanical energies to electricity using triboelectrification is one of the emerging technologies. Triboelectric nanogenerators (TENGs) have drawn much attention due to their high conversion efficiency. However, the internal capacitance of TENGs limits the currents generated and slows down the charging rate of storage elements. Such limitations restrict the amount of the generated power and the application of TENGs in areas that need high currents and power. This paper presents a solution to enhancing the output power of a TENG by devising an active on chip (IC) matching circuit. The matching circuit generates a negative capacitance to counter the effect of TENG’s internal capacitance and boosts the produced current. We implement the circuit using 130 nm CMOS technology and use a part of the generated power to provide the circuit with the needed biasing. The performance of the matching circuit is tested at different values of load capacitances. A relationship between the load and parasitic capacitances is estimated, which agrees with the simulation results. Numerical simulations show that the generated power can be greatly improved by using the matching circuit for four types of TENGs. The proposed matching circuit only consumes 6 . 4 μ W and improves the power of the TENG by 77.9% on average. • A matching architecture to improve the power generated from triboelectric nanogenerators using an active inductor circuit. • Implementing a negative impedance converter with low power consumption to generate a negative capacitance as a solution for creating an active inductor. • The matching circuit will be supplied by a small amount from the power generated from the TENG to achieve a fully integrated matching system that requires no external biasing source.

Highly sensitive SWIR detector array based on nanoscale phototransistors integrated on CMOS readout

Ultra-sensitive and fast infrared imaging has become increasingly important in applications that require high frame rates at low light levels, such as exoplanet imaging. The sensitivity of conventional short-wave infrared cameras is limited by their readout noise level. This limitation can be addressed by the internal gain of the sensors, but only if fast response time and low dark current are achieved simultaneously. Recent theoretical predictions suggested that reducing the internal capacitance of detectors with internal gain can increase their sensitivity. Here, we show the experimental validation of this prediction for III–V heterojunction phototransistors. We have fabricated a 320 × 256 array of InGaAs/InP infrared phototransistors integrated with a conventional silicon readout circuit. The array is made of two groups of pixels: 50% are devices with a 1 μm base diameter and the other 50% with a 2 μm base diameter. Characterization of a large number of pixels shows that 1 μm devices have significantly higher sensitivity than 2 μm devices. These have an average noise equivalent photon sensitivity of about 20 photons at a camera frame rate of ∼500 frames per second, which is better than the best existing infrared cameras with a similar cutoff wavelength and frame rate. Interestingly, the processing variation in the 1 μm devices resulted in variation in sensitivity, and a good number of devices show sensitivity to less than 10 photons. These results suggest that the proposed phototransistors are promising for ultra-sensitive short-wavelength infrared cameras.

Colossal permittivity of (Gd + Nb) co-doped TiO2 ceramics induced by interface effects and defect cluster

Material with high dielectric constant plays an important role in energy storage elements. (Gd + Nb) co-doped TiO2 (GNTO) ceramics with giant dielectric permittivity (>104), low dielectric loss, good temperature and frequency stability in broad range of 30–150 °C and 102–106 Hz have been systematically characterized. Especially, a low dielectric loss of 0.027 and a giant dielectric permittivity of 5.63 × 104 at 1 kHz are attained for the composition with x = 0.01. Results of complex impedance spectroscopy, I–V curve and frequency dependent dielectric constant under DC bias indicate that internal barrier layer capacitance (IBLC) effect, electrode effect and electron-pinned defect-dipole (EPDD) effect contribute to the colossal permittivity (CP) property simultaneously.

Microbial fuel cell soft sensor for real-time toxicity detection and monitoring.

Real-time toxicity detection and monitoring using a microbial fuel cell (MFC) is often based on observing current or voltage changes. Other methods of obtaining more information on the internal state of the MFC, such as electrochemical impedance spectroscopy (EIS), are invasive, disruptive, time consuming, and may affect long-term MFC performance. This study proposes a soft sensor approach as a non-invasive real-time method for evaluating the internal state of an MFC biosensor during toxicity monitoring. The proposed soft sensor approach is based on estimating the equivalent circuit model (ECM) parameters in real time. A flow-through MFC biosensor was operated at several combinations of carbon source (acetate) and toxicant (copper) concentrations. The ECM parameters, such as internal resistance, capacitance, and open-circuit voltage, were estimated in real time using a numerical parameter estimation procedure. The soft sensor approach proved to be an adequate replacement for EIS measurements in quantifying changes in the biosensor internal parameters. The approach also provided additional information, which could lead to earlier detection of the toxicity onset.

Synthesis of the hollandite-like copper doped potassium titanate high-k ceramics

The hollandite-like copper doped potassium titanate was synthesized by two-step method, including the potassium polytitanate precursor modification with copper compounds in aqueous solution and the following calcination at 900 °C. The structure of material obtained was studied using the XRD and SEM analysis. The Rietveld method was used to estimate the crystalline unit cell parameters and calculate the exact stoichiometry of K1.53(Cu0.76Ti7.24)O16 by refining the atomic occupancies for chemical elements. High-k ceramic materials based on this shollandite-like solid solution were sintered at different temperatures varied in the range from 1000 to 1100 °C. The influence of sintering conditions on electric properties of the obtained ceramics was investigated in a wide frequency range. The contribution of different processes on permittivity was discussed using the electron-pinned defect-dipole (EPDD) model, and the internal barrier layer capacitance (IBLC) model. The optimal conditions to produce modified potassium polytitanate, used as intermediate, as well as optimal sintering conditions which allowed obtaining mono-phase hollandite-like ceramic materials were recognized. It was found that such ceramic materials had high permittivity (ε’ ≈ 0.9 × 104 at 10 Hz).

Colossal permittivity and multiple effects in (Zn + Ta) codoped TiO2 ceramics

ABSTRACT Colossal permittivity (CP) materials are potential for the important applications of device miniaturization and energy storage. In this work, (Zn2+ 1/3Ta5+ 2/3)xTi1-xO2 ceramics were fabricated by conventional solid-state method. Large dielectric permittivity (>104) and low tanδ (<0.06) have been attained. This dielectric property shows a high stability in wide temperature (30–200°C) and frequency (20–106 Hz) range. The crystalline structure, microstructure and dielectric properties of ZTTO ceramics were systematically investigated. XPS reveals the formation of electron-pinned defect-dipoles (EPDD) model. In addition, combined with impedance spectroscopy and frequency dependent dielectric constant under DC bias results reveal that colossal permittivity are mainly caused by EPDD model, internal barrier layer capacitance (IBLC) effect, and electrode effect. This work would provide guidance to further researching the colossal permittivity materials.

True Random Number Generation Using Latency Variations of FRAM

True random number generation (TRNG) plays an important role in security applications and protocols. In this article, we propose an effective technique to generate a robust true random number using emerging, energy-efficient, nonvolatile, consumer-off-the-shelf (COTS) ferroelectric random access memory (FRAM) chips. In the proposed method, we extract inherent randomness from internal ferroelectric capacitors by exploiting latency variation across cells within FRAM. Hardware results and subsequent National Institute of Standards and Technology (NIST) statistical test suite (STS) testing indicate that the proposed latency-based TRNG is robust over a wide range of operating conditions at speeds of 6.23 Mb/s using COTS, silicon FRAM chips from Cypress Semiconductor Corporation.

Studies on Dynamic Properties of Ultracapacitors Using Infinite r–C Chain Equivalent Circuit and Reverse Fourier Transform

The specific power storage capabilities of double-layer ultracapacitors are receiving significant attention from engineers and scientific researchers. Nevertheless, their dynamic behavior should be studied to improve the performance and for efficient applications in electrical devices. This article presents an infinite resistor–capacitor (r–C) chain-based mathematical model for the analysis of double layer ultracapacitors. The internal resistance and capacitance were measured for repetitive charging and discharging cycles. The magnitudes of internal resistance and capacitance showed approximately ±10% changes for charge-discharge processes. Electrochemical impedance spectroscopy investigations revealed that the impedance of a double-layer ultracapacitor does not change significantly in the temperature range of (−30 °C to +30 °C) and voltage range of (0.3376–2.736 V). The analysis of impedance data using the proposed mathematical model showed good agreement between the experimental and theoretical data. The dynamic behavior of the ultracapacitor was successfully represented by utilizing the proposed infinite r–C chains equivalent circuit, and the reverse Fourier transform analysis. The r–C electrical equivalent circuit was also analyzed using the PSIM simulation software to study the dynamic behavior of ultracapacitor parameters. The simulation study yields an excellent agreement between the experimental and calculated voltage characteristics for repetitive charging-discharging processes.

Development of Statistical Model for Selection of Electrode Parameters in Manufacturing of Ultracapacitor

Ultracapacitor is a new electrical energy storage device which has high power density than conventional battery and capacitor. It offers high capacitance in small volume compared to conventional capacitors. While selecting ultracapacitors for various applications, parameters like specific resistance, internal capacitance, pulse current, energy density are required to be considered. Amongst these factors, specific capacitance of ultracapacitor depends mainly on parameters of electrode. The present paper is focused on modeling of ultracapacitor based on variations in some of the electrode parameters. The objective of present research work is to apply a statistical method to obtain an electrode material based model for prismatic type ultracapacitor. To have deep insight about the performance through modeling approach, the number of trials have been taken by doing the variations in the electrode materials of ultracapacitor and the quantity of the electrode material loaded on the current collector. The effect of both these variations is studied over the specific capacitance, which is taken as output parameter of model. Developed model is validated at selected values of input parameters.