Inter-metal Dielectric Layer Research Articles

Prevention of plasma-induced damage during HDP–CVD deposition

The high-density plasma (HDP)–chemical vapor deposition (CVD) process consists of a simultaneous sputter etch and chemical vapor deposition. As the CMOS process continues to scale down to sub-quarter micron technology, the HDP process has been widely used for the gap-fill of small geometry metal spacing in the inter-metal dielectric (IMD) process. However, the HDP–CVD system has some potential problems including plasma-induced damage. Plasma-induced gate oxide damage has become an increasingly important issue for integrated circuit process technology. In this paper, the thin gate oxide charge damage caused by the HDP deposition of IMD layer was studied. As an experimental result, the multiple step of HDP deposition process was prevented the plasma-induced damage by introducing an in situ top SiH 4 unbiased liner deposition before conventional deposition.

Advantages of point of use (POU) slurry filter and high spray method for reduction of CMP process defects

As integrated circuit devices shrink to smaller dimensions, a chemical mechanical polishing (CMP) process was required for the global planarization of the inter-metal dielectric (IMD) layer with free-defects. However, as the IMD layer gets thinner, micro-scratches are becoming a major defect. Micro-scratches are generated by agglomerated slurry, solidified and attached slurry in the pipeline of the slurry supply system. In order to prevent the agglomerated slurry particles from slurry inflow, we installed a 0.5 μm point of use (POU) filter, which is a depth-type filter and has 80% filtering efficiency for 1.0 μm size particles. Also a high spray bar of de-ionized water with high pressure was installed in the CMP equipment. Our experimental results showed that it is impossible to completely prevent defect-causing particles through the depth-type filter. Thus, we suggest that it is necessary to optimize the slurry flow rate and to install a high spray bar of de-ionized water (DIW) with high pressure, in order to overcome the weak points of a POU depth-type filter.

Reduction of process defects using a modified set-up for chemical mechanical polishing equipment

The chemical mechanical polishing (CMP) process is widely used for global planarization of inter-metal dielectric (IMD) and inter-layer dielectric (ILD) layers for deep sub-micron technology. However, as the IMD and ILD layers get thinner, defects such as micro-scratches can lead to severe circuit failure, which affects yield. In this paper, for the improvement of the CMP process, deionized water (DIW) pressure, purified nitrogen (PN 2) gas, point of use slurry filter, and high spray bar were installed. Our experimental results show that DIW pressure and PN 2 gas factors are not related to removal rate, but they are closely related to the edge hot spot on a patterned wafer. Also, the filter installation in a CMP instrument could remarkably reduce the defects after CMP processing, it is shown that the slurry filter plays an important role in the determination of pad lifetime. However, since the slurry filter cannot completely prevent defect-causing particles from entering the system, the installation of the high spray bar of deionized water with high pressure is proposed.

Failure Analysis for High via Resistance by HDP CVD System for IMD Layer

As the application of semiconductor chips into electronics increases, it requires more complete integration, which results in higher performance. And it needs minimization in device design for cost saving of manufacture. Therefore oxide gap fill has become one of the major issues in sub-micron devices. Currently HDP (High-Density Plasma) CVD system is widely used in IMD (Inter Metal Dielectric) to fill narrower space between metal lines. However, HDP-CVD system has some potential problems such as plasma charging damage, metal damage and etc. Therefore, we will introduce about one of via resistance failure by metal damage and a preventive method in this paper.

Effects of Various Facility Factors on Chemical Mechanical Polishing Process Defects

The chemical mechanical polishing (CMP) process is widely used for the global planarization of the inter-metal dielectric (IMD) layer and inter-layer dielectric (ILD) for deep sub-micron technology. However, as the IMD layer and ILD become thinner, defects such as micro-scratches can lead to severe circuit failure, which affects yield. In this study, for the improvement of the CMP process, de-ionized water (DIW) pressure was varied, purified nitrogen (PN2) gas was used, and a point of use (POU) slurry filter and high spray bar (HSB) were installed. Our experimental results show that DIW pressure and PN2 gas factors were not related to removal rate, but the edge hot spot of the patterned wafer had a marked effect. Also, the filter installation in the CMP polisher could remarkably reduce the number of defects after CMP processing, thus it is shown that the slurry filter plays an important role in determining pad lifetime. However, the slurry filter cannot eliminate defect-causing particles completely. Thus, we suggest that it is necessary to install a high spray bar of de-ionized water (DIW) with high pressure, to overcome the weak points of a slurry filter.

Improvements of CMP characteristics using slurry filter and high-spray bar of de-ionized water

As the integrated circuit device size shrinks to smaller dimensions, a chemical mechanical polishing (CMP) process was required for the global planarization of inter-metal dielectric (IMD) layer free of defects. However, as the IMD layer gets thinner, micro-scratches are becoming a major concern. Micro-scratches are generated by agglomerated slurry, solidified and attached slurry in the pipe-lines of the slurry supply system. In order to prevent the agglomerated slurry particles from slurry inflow, we installed a 0.5-μm point-of-use (POU) filter, which is a depth-type filter and has 80% filtering efficiency for the 1.0-μm size particles. Also, a high-spray bar of de-ionized water with high pressure was installed in the CMP equipment. In this paper, we studied the relationship between defect generation and pad counts to understand the exact efficiency of the slurry filter, and to determine the appropriate pad usage. Our experimental results showed that it is impossible to prevent defect-causing particles completely through the depth-type filter. Thus, we suggest that it is necessary to optimize the slurry flow rate and to install a high-spray bar of de-ionized water (DIW) with high pressure, in order to overcome weak points of the POU depth-type filter.

A study of the influence of inter-metal dielectrics on electromigration performance

The relative electromigration performance of test structures with a common Ti/TiN–Al–1% Cu–TiN metallization scheme and with three different inter-metal–dielectric (IMD) layers is compared. Differences in lifetimes are observed which are attributable to the influences of the different IMD layers. The IMD layers in question are (a) polyimide, (b) a flexible inorganic dielectric layer, and (c) a rigid inorganic dielectric layer. A matrix of conventional electromigration tests has been carried out. The possible influence of stress migration is investigated and an explanation for the relative behaviour is proposed.

Deposition of stable, low κ and high deposition rate SiF 4-doped TEOS fluorinated silicon dioxide (SiOF) films

Fluorine doped silicon dioxide (SiOF) is recognized as a potential intermetal dielectric (IMD) film for sub-half micron devices, due to its low dielectric constant ( κ) and good gap-fill capabilities. For the first time, physically stable and high deposition rate (1550 nm/min) SiOF films were deposited using a parallel-plate plasma CVD–single wafer DxZ reactor, involving SiF 4/TEOS/O 2 chemistry. The analytical results indicate that these SiOF films, having a F concentration up to 3.0%, contain only Si–F bonding, do not absorb moisture and show stable dielectric constants. A typical highly stable SiOF film has F concentration and dielectric constant values of 2.4% and 3.5, respectively. This film is thermally stable up to 600°C and can be used as a low cost cap layer for HDP–CVD oxides and other low κ spin-on-glass materials, as well as an IMD layer for damascene applications.

Thermal Stability Study of the Interconnect System with Fluorinated Silicate Glass as IMD Layers

AbstractWhile fluorinated silicate glass (FSG) has been proposed for low k inter-metal dielectric (IMD) applications in a multi-level interconnect system either as the only IMD material, or as one of the materials for a multi-layer IMD system, thermal stability of the FSG film and its impact on device reliability remain a concern for this application. In this study, SIMS, SEM, and optical microscope analyses were carried out to evaluate the thermal stability of the FSG films and the possible reactions between FSG and metals. It was observed that at elevated temperatures fluorine tends to diffuse into an undoped oxide film rather than be desorbed. The data indicate that F diffuses 3.5 times faster in a silicon oxide film than in a silicon nitride film. Sub-half micron devices were processed with FSG as IMD layers. The devices were tested using an intensive thermal stability test methodology. A TiSi2 reaction with F which diffused from the FSG film was observed under optical microscopy. This reaction caused TiSi2 delamination. Electrical characterization of devices was performed before and after the thermal stability test. Although the device performance did not change greatly, the reaction certainly affects the long term device reliability (vide infra). Barrier materials were investigated to solve the F diffusion problem. With the proper diffusion barrier, the problem of the fluorine reaction with TiSi2 and subsequent metal blistering was eliminated.

Elimination of Al Line and Via Resistance Degradation under HTS Test in Application of F-Doped Oxide as Intermetal Dielectric

Fluorine-doped silicon oxide (SiOF) as intermetal dielectric (IMD) layer was deposited by conventional plasma-enhanced chemical vapor deposition (CVD). The main issues in the application of SiOF as IMD are as follows: (1) instability of film properties such as stress and refractive index during HTS test, (2) desorption of H2O and HF gases from SiOF film, (3) increase of line resistance, (4) wedgelike defects of metal lines, and (5) via resistance degradation during HTS test at 350°C. The above problems in use of SiOF as IMD can be eliminated by the passivation of IMD with PE-SiN and the application of Ti underlayer before the second metal deposition.

Double-sided double-metal AC-coupled silicon microstrip detectors

Novel silicon microstrip detectors, which combine double side operation, on-chip coupling capacitors and two levels of metallization have been developed, manufactured and tested. This approach aims at very low mass system assemblies, particularly important for applications in vertex detection at LEP and at future B-factories. Devices were integrated on 100 mm diameter silicon wafers on which several dielectrics for AC coupling were tested. A SiO2Si3N4 double dielectric layer, etched between strips, performed best with respect to leakage current, breakdown voltage and oxide integrity. In order to minimize stray capacitance between strips in the 2 metal layers, an extremely thick (5.2 μm) intermetal dielectric layer was used. A special photolithographic and etching process which guarantees good step coverage was developed, resulting in tapered vias.Static measurements were carried out on detectors of various dimensions. Leakage current, depletion voltage and capacitive effects from cross-coupling between metal 1 and metal 2 were measured. In particular, the breakdown characteristics of the coupling capacitor formed by the implanted strips and the metal 1 strips were investigated for several insulators. With the SiO2Si3N4 double dielectric layer, a pinhole density of the order of 1% was obtained for some of the detectors, with leakage currents of around 100 nA/cm2. The connectivity between metal 1 and metal 2 layers was found to be excellent. The dynamic response of the detectors was studied using the VIKING front-end readout chip.The results show that these complex double-sided chips, which are required for next generation detectors, are reaching a state of maturity.

Gravimetric measurements of steady‐state moisture uptake in spin‐coated polyimide films

AbstractPolyimide (PI) is an insulating polymer that is finding increased use in the semiconductor industry as an intermetal dielectric, passivation coating, and planarization layer. It has a low dielectric constant (3.5 at audio frequencies) and can be processed at temperatures below 450°C. These features make PI attractive to the integrated circuit industry. One disadvantage of this material is that, like most polymers, it is hygroscopic. Moisture can lead to such reliability problems in integrated circuits as increased insulator conductivity, loss of adhesion, and corrosion. It is important to quantify the moisture uptake in polyimide so that the reliability implications of its use can be fully understood. In this study, the steady‐state moisture uptake of the model PI pyromellitic dianhydride‐oxydianiline (PMDA‐ODA) is reported. The moisture uptake is measured using a Cahn 1000 Microbalance with a 1‐μg resolution. The samples are prepared by spin‐coating one or more layers of the precursor polyamic acid onto 2‐in silicon substrates. The moisture uptake in these polymers is found to be linearly related to ambient relative humidity, and the maximum moisture uptake by weight is 3.2%. The moisture uptake in PI is also shown to be a bulk absorption rather than a surface adsorption phenomenon.

4956604 Broad band contactor assembly for testing integrated circuit devices

A micromachining technology for integrating high-performance radio-frequency (RF) passives on CMOS-grade low-cost silicon substrates is developed. The technology can form a thick solid-state dielectric isolation layer on silicon substrate through high-aspect-ratio trench etch and refill. On the non-high-resistivity but low-loss substrate, two metal layers with an inter-metal dielectric layer are formed for integrating embedded RF components and passive circuits. Using the technology, two types of integrated RF filters are fabricated that are band-pass filter and image-reject filter. The band-pass filter shows measured minimum insertion loss of 3.8 dB and return loss better than 15 dB, while the image-reject filter exhibits steeper band selection and achieves better than −30 dB image rejection. A 50 Ω co-planar waveguide (CPW) on the substrate is also demonstrated, showing low loss and low dispersion over the measured frequency range up to 40 GHz. The developed technology proves a viable solution to implementing silicon-based multi-chip modules (MCM) substrates for RF system-in-package (RF-SiP).

Hollow cathode deposition of silicon dioxide films

Intermetal dielectric layers in integrated circuits must be formed at low temperatures and with controlled surface morphology. Some important vacuum processes used for such depositions include bias sputtering and bias chemical vapour deposition. These processes yield planarized layers but often result in very low deposition rates and high levels of damage in underlying devices. In this paper we describe the application of a hollow cathode deposition system to the high rate deposition of planarized silicon oxide films at relatively low target voltages. This system is also of interest because its mirror field minimizes electron bombardment, and hence promises low X-ray damage levels. In this study, a 120 mm diameter target hollow cathode system has been used to study SiO x deposition from SiH 4-N 2O and SiH4 O 2 gas mixtures over a range of operating conditions. Some of these results are compared with those obtained in an asymmetric diode system. It is found that the deposition rate in the hollow cathode is up to 4 times that of the diode for the same input power, and up to 10 times the diode rate for the same applied voltage, all at pressures below 5 Pa. Good void filling and surface planarization has been produced in 1:1 aspect ratio submicron structures. Thickness uniformities of ±3% over a 95 mm diameter and refractive indices of between 1.45 and 1.47 over the substrate surface have been measured. These figures are limited only by the present simple gas feed system. Wet chemical etch rates and electrical breakdown strength are almost the same as thermal SiO 2. Similarly, preliminary Fourier transform IR spectra have displayed Si-O peak positions the same as those of thermal oxide controls. Initial C-V measurements suggest that a fixed oxide charge of about 3 × 10 12 cm −2 is formed with the present operating parameters. Annealing at 750°C reduces this charge to a value of 7.5 × 10 11 cm −2