Prevention of plasma-induced damage during HDP–CVD deposition

Abstract

The high-density plasma (HDP)–chemical vapor deposition (CVD) process consists of a simultaneous sputter etch and chemical vapor deposition. As the CMOS process continues to scale down to sub-quarter micron technology, the HDP process has been widely used for the gap-fill of small geometry metal spacing in the inter-metal dielectric (IMD) process. However, the HDP–CVD system has some potential problems including plasma-induced damage. Plasma-induced gate oxide damage has become an increasingly important issue for integrated circuit process technology. In this paper, the thin gate oxide charge damage caused by the HDP deposition of IMD layer was studied. As an experimental result, the multiple step of HDP deposition process was prevented the plasma-induced damage by introducing an in situ top SiH 4 unbiased liner deposition before conventional deposition.