Interlayer Dielectric Film Research Articles

Effect of substrate on the step coverage of plasma-enhanced chemical-vapor deposited tetraethylorthosilicate films

Plasma-enhanced chemical-vapor deposition tetraethylorthosilicate (TEOS) films are extensively used as the interlayer dielectric films in multilevel interconnection processes. When TEOS oxide films were deposited on metal patterns three different substrates, titanium nitride (TiN), aluminum (Al), and oxide (SiO2), were used. This study examines the dependence of these substrates on TEOS step coverage. The deposition rates of TEOS oxide revealed that the SiO2 substrate lead to highest TEOS deposition rate during the initial deposition period of 5 s. Then, the TEOS deposition rate of the substrates was nearly the same. The TiN substrate exhibited the highest sidewall step coverage but the sidewall step coverage of the Al substrate deteriorated due to its granular surface. Additionally, different substrates exhibited different coverage of the bottom step. Moreover, the bottom step coverage exceeded the sidewall coverage for all substrates.

The Effects of Dilution Gas and Pressure on the Properties of PE-CVD Low-k Film

Low-k interlayer dielectric film with a relative dielectric constant (k) of 2.6 has been formed by plasma enhanced chemical vapor deposition (PE-CVD) with hexamethyldisiloxane (HMDSO), nitrous oxide, and dilution gases. The effect of the dilution gases on the vapor phase reaction, the deposition rate, the electrical property, the thermal stability, the structure, and the mechanical property of the PE-CVD low-k film were clarified. The vapor phase reaction in helium dilution gas hardly occurs compared with argon and nitrogen. However, the deposition rate using He dilution gas is smaller than that using either of the other two dilution gases. Ammonia ions were found to be contained in much greater quantities in the film deposited using dilution gas than in the film deposited using He and Ar dilution gases by thermal desorption spectroscopy. The pressure effect on the composition of the low-k film was also clarified. Hydrogen content in the low-k film increases with increasing deposition pressure. © 2002 The Electrochemical Society. All rights reserved.

Application for WLP at positive working photosensitive polybenzoxazole.

We have developed a positive working photosensitive polybenzoxazole (PBO) for semiconductor surface coating material. Now it has already been used for buffer coat to protect electrical circuit on IC chip in the semiconductor market. Cure film of this photosensitive PBO has not only low water absorption (0.3%) and low dielectric constant (2.9) but also high adhesion to substrate such as SiO2 etc. And the patterning profile has suitable taper shape after development and curing. These properties are useful for application of interlayer dielectric film for Multi Chip Module (MCM ) package and Wafer Level Package (WLP).

Developments of new concept analytical instruments for failure analyses of sub-100 nm devices

We have developed analytical instruments based on new concepts for failure analyses of devices of 100 nm dimensions or less. They are a sputtered neutral mass spectrometer with focused ion beam for highly sensitive element analysis in microarea (10 18 atoms/cm 3 in 30 nm area), transmission electron microscope (TEM) with electron energy loss spectrometer for chemical bond analysis in less than 2 nm area, Nanoprober for electrical characteristics inspection in actual circuits, computed tomography-TEM for three-dimensional observation of crystalline defect with 1 nm spatial resolution, atmospheric pressure ionization mass spectrometer for trace impurities ppq (parts per quadrillion) analysis in gases, and glow discharge optical emission spectrometer for rapid and precise composition analysis. Using these instruments, it was found that the formation of SiO 2 or TiO x film by water from titanic acid (TiO x ·H 2O) is the cause of the high resistivity in a contact (CVD-W/CVD-TiN/Ti/Si) and vaporization of silicon dioxide by phosphorus trifluoride (PF 3) is the cause of voids in interlayer dielectric film borophosphosilicate glass.

Electromigration and electrochemical reaction mixed failure mechanism in gold interconnection system

Power bipolar devices with gold metallization experience high failure rates. The failures are characterized as shorts, detected during LSI testing at burn-in. Many of these shorted locations in the chip are the same for the failed devices. From a statistical analysis for wafer lots, it is found that the short failure rate is higher for the lots with thinner SiON interlayer dielectric films. Cracks are commonly observed in the SiON films at step edge portions of the device. The SiON film is locally turned to Au–Si eutectic at short positions by the reaction of Au with the SiON film and the reaction is only generated at specific step edge portions, i.e., at step edge on emitter electrodes in driver transistors and/or at cross-points of power lines. Based upon these results, a new electromigration and electrochemical reaction mixed failure mechanism is proposed for the failure.

Direct patterning of photosensitive low-dielectric-constant films using electron-beam lithography

A direct patterning technique of interlayer dielectric films was developed for multilevel interconnections. A photosensitive methylsilazane film with a dielectric constant of 2.7 was synthesized. A methylsilazane precursor consists of a photoacid generator, a sensitizer, and a base polymer. The photosensitive methylsilazane film could be patterned by use of electron-beam lithography or ultraviolet lithography. It was demonstrated that the smallest feature size of 50 nm for damascene lines and via holes could be directly patterned in these films by electron-beam lithography.

A study on dielectric properties of a new polyimide film suitable for interlayer dielectric material in microelectronics applications

Interlayer dielectric film formation under Al wirings for VLSI and ULSI devices requires low temperature processing and high surface planarization capability. Polymers as a dielectric material play a significant role in achieving the current state-of-the art in microelectronics.In this work, the dielectric properties of a new polyimide material suitable for microelectronics applications have been investigated. The polyimide was synthesized following the synthesis of 4,4′-bis(3-aminophenoxy)diphenyl sulfone (DAPDS), by nucleophilic aromatic substitution of 4,4′-dichlorodiphenyl sulfone with m-aminophenol, DAPDS/pyromellitic dianhydride (PMDA). Using this specific polyimide, a metal–polyimide–silicon (MIS) structure was manufactured to demonstrate the dielectric properties of the material. The properties of the MIS capacitance have been examined by deriving an electrical model of the MIS structure.

Material Properties of a SiOC Low Dielectric Constant Film with Extendibility to k < 2.7

AbstractA plasma deposited SiOC very low k (VLK) interlayer dielectric (ILD) film has been developed which can be tuned to 2.5 = k = 3.0, demonstrates very good thermal stability, excellent adhesion properties, acceptable hardness, and an indication that it may be extendible to k < 2.5. This paper will disclose properties of this SiOC film which are important to a VLK ILD application.

Process optimization of dielectrics chemical mechanical planarization processes for ultralarge scale integration multilevel metallization

The requirements of gap-fill and global planarization for interlayer dielectric films obtain more and more importance as the size of the integrated circuits shrinks. Typical dimensions are 0.35 μm for gaps between 0.7 μm high aluminum interconnect lines with an aspect ratio of 2:1. The push of leading edge ultralarge scale integration manufacturing technologies toward the formation of sub 0.1 μm feature sizes places extreme performance demands on the processes and equipment used. At submicron linewidths, the depth-of-focus was limiting technology and chemical mechanical planarization (CMP) became a necessary tool for feature sizes of 0.35 μm and below. Thus, CMP emerged quickly and has become quite sophisticated [R. DeJule, Semicond. Int. 11, 15 (1996)]. Also, in order to fill the small feature sizes high-density plasma chemical vapor deposition (HDP–CVD) of insulators gained increasing attention in the semiconductor world. Due to the uniform thickness of the HDP intermetal dielectric (see Fig. 1) the polishing time is shortened, pad wear is reduced, and thus, increasing the intervals between pad dressing. An increased throughput, as well as extended CMP stability and repeatability can be achieved. A saving in processing time as compared to standard techniques up to 35% is possible. In this article we describe the major dependencies of machine parameters versus experimental results for different CMP processes.

Low dielectric constant materials and methods for interlayer dielectric films in ultralarge-scale integrated circuit multilevel interconnections

This paper reviews low dielectric constant materials for interlayer dielectric films in ultralarge-scale integrated circuit (ULSI) multilevel interconnections. The trends of ULSIs in the last decade were briefly described first. Then, the requirements for interlayer dielectric film properties and their formation techniques were explained. They are: (1) a low dielectric constant, (2) a surface planarity, (3) a gap-filling capability, and (4) a low residual stress. In contrast with the requirements, the interlayer dielectric films and related technologies developed in the last decade were reviewed. In the requirements, the low dielectric constant materials are strongly required because the device performance has been limited by signal propagation time and cross-talk in the multilevel interconnections. Furthermore, the low dielectric constant is also required for reduction of power consumption in ULSI operation. Finally, the low dielectric constant materials were summarized, and future trends of the low dielectric constant interlayer dielectric film technologies are discussed.

An SiO2 Film Deposition Technology Using Tetraethylorthosilicate and Ozone for Interlayer Metal Dielectrics

A void‐free interlayer dielectric film formation technology has been developed. This technology utilizes tetraethylorthosilicate [TEOS, ]/ozone atmospheric pressure chemical vapor deposition (APCVD) film gap‐filling, and the TEOS‐based dual frequency plasma enhanced vapor deposition (PECVD) film as an underlayer of APCVD film. This technology enables the formation of void‐free interlayer dielectric films without any pretreatment for the underlayer between aluminum wirings line and space of 600 and 600 nm, respectively. Single‐frequency PECVD films are also applied as an underlayer of APCVD gap‐filling. However, void‐free gap‐filling cannot be achieved, even using the single frequency PECVD underlayer. To clarify the mechanism of the void‐free gap‐filling, the underlayer PECVD film properties are investigated. The film density at the Al wiring pattern's sidewall of the dual‐frequency PECVD films is equal to that at the pattern's bottom, while the density at the pattern's sidewall formed using single‐frequency PECVD films is lower than that at the pattern's bottom. The carbon concentration for the dual‐frequency PECVD films is lower than that for the single‐frequency PECVD films. The and acetaldehyde detected from the dual‐frequency PECVD films due to the oxidation of the ethoxy group, is much more than that from the single‐frequency PECVD films. Based on the experimental results, the mechanism of void‐free gap‐filling of APCVD films is considered to consist of three steps; (i) involving R ions (R, alkyl group) into the PECVD films during film deposition, (ii) Si‒OR bonds formation at the PECVD films' surface, and (iii) oligomers flow at APCVD film deposition. It is considered that the oligomers flow is promoted by the Si‒OR bonds, resulting in the void‐free gap‐filling. The dual‐frequency PECVD films can improve the gap‐filling of APCVD films.

Instability of Si—F bonds in fluorinated silicon oxide (SiOF) films formed by various techniques

Instability of Si—F bonds in fluorinated silicon oxide (SiOF) films is studied. Al wiring corrosion and underlayer SiO2 etching problems are the major issues for the use of SiOF interlayer dielectric films. To clarify the mechanism, three kinds of SiOF films have been used for this study. They are: (i) a fluorinated silicon oxide (SiOF) film prepared by room-temperature chemical vapour deposition (RTCVD) using fluorotriethoxysilane and pure water as gas sources; (ii) a fluorinated spin-on-glass (SOG) film prepared by fluorotrialkoxysilane vapor treatment (FAST); and (iii) a room-temperature liquid phase deposition (LPD) SiOF film. The initial refractive indices for the RTCVD-SiOF, FAST-SOG and LPD-SiOF films are 1.400, 1.398 and 1.433, respectively. After conducting a pressure cooker test (PCT) at 125 °C for 520 h, the refractive indices for the RTCVD-SiOF, FAST-SOG and LPD-SiOF films increase to 1.450,1.440 and 1.436, respectively. The Si—O bond peak absorption coefficient for the LPD-SiOF film decreases at the early stage of PCT, but those for the RTCVD-SiOF and FAST-SOG films increase at the early stage of PCT. The initial Si—F bond peak absorption coefficient for the RTCVD-SiOF film is much higher than those for the LPD-SiOF and FAST-SOG films. It decreases drastically in the PCT time ranging from 0 to 140 h. The Si—F bond peak absorption coefficients for the FAST-SOG and LPD-SiOF films show a slow reduction, as compared with that for the RTCVD-SiOF film at the early stage of PCT. Although the OH peak absorption coefficients for the RTCVD-SiOF and FAST-SOG films increase at the early stage of PCT and level off at 50 h, that for the LPD-SiOF film increases at 306 h. After conducting 520 h PCT, concentrations of fluorine atoms for the RTCVD-SiOF and FAST-SOG films decrease by three orders and two orders of magnitudes, respectively. However, the LPD-SiOF film has a limited change in the fluorine concentration, as compared with those for the RTCVD-SiOF and FAST-SOG films. The thicknesses for all of the films remain almost unchanged after PCT for 520 h.

Formation of SiOF Films by Plasma-Enhanced Chemical Vapor Deposition Using (C2H5O)3SiF

A new Plasma-Enhanced Chemical Vapor Deposition (PECVD) method using (C2H5O)3SiF: tri-ethoxy-fluoro-silane as an interlayer dielectric film is proposed based on considerations of gas chemistry. RF power dependence of the film characteristics is investigated, and it is clarified that fluorine stability is improved with increasing RF power. The relative dielectric constant of the films deposited at the power of more than 700 W is about 3.5. Moisture absorption of the film formed from TEFS at 900 W is smaller than that of the SiOF film formed from C2F6 added TEOS.

A test chip design for detecting thin-film cracking in integrated circuits

A reliability problem associated with integrated circuit assembly in molded plastic packages involves cracking in the deposited thin film layers on the top silicon surface. During thermal cycle testing, thermomechanical stresses resulting from differences in expansion coefficient can cause large relative displacements at the silicon/mold compound interface. The resulting die surface shear stresses are heavily concentrated at the corners and edges of the silicon die. These shear stresses can result in critical stress concentrations in the brittle passivation and interlayer dielectric films. This paper will report on a test chip design involving a matrix of crossing metal traces. This test chip has been designed to be sensitive to electrical leakage problems associated with thin film cracking. Two important quantities are measured. The first is electrical failure rate, which is determined as a function of metal width and proximity to the corners and edges of the die. The second is the extent over which cracking in the thin film layers progresses into the interior of the die. When overlaid on simple linear elastic finite elements models of stress, this locus of failure tends to follow lines of constant shear stress. This allows the assignment of a nominal stress value, critical in the collapse of microscopic thin film structures.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Fluorinated interlayer dielectric films in ULSI multilevel interconnections

Fluorinated interlayer dielectric films for ultra large scale integrated circuit (ULSI) multilevel interconnections are investigated. The interlayer dielectric film properties and their formation techniques have to meet three requirements such as: (1) a high planarization capability, (2) a low dielectric constant and (3) a low deposition temperature. To satisfy the three requirements, the technologies such as (i) a fluorinated spin-on-glass (SOG) film by fluorotrialkoxysilane vapor treatment (FAST-SOG), (ii) a fluorinated SiO 2 (SiOF) film by room temperature chemical vapor deposition (RTCVD-SiOF) using fluorotrialkoxysilane (FTAS) and pure water as gas sources, (iii) a room temperature liquid phase deposition (LPD) SiO 2 film, and (iv) fluorinated polyimide siloxane (F-PSI) films are desirable. The RTCVD, FAST and LPD techniques have shown the possibility to reduce the film formation temperature to room temperature by catalytic reactions. The dielectric constant for SiO 2 films can be reduced to 3.7 at 1 MHz by using the RTCVD and LPD techniques. The dielectric constant of 2.7 at 1 MHz can be achieved for the F-PSI films, and is lower than those for conventional polyimide films (3.2–3.5) and SiO 2 films (3.9–4.2). Although the FAST-SOG, RTCVD-SiOF and F-PSI films cannot achieve full planarization, the LPD technique can achieve both global and local planarization because this technique has high capability for selective SiO 2 film deposition. The fluorinated films have other good properties such as low residual stress, low residual OH contents and low moisture absorption, which can enlarge the fabrication margins of multilevel interconnections. These other properties are also very effective for improving the ULSI devices performance.

Ammonium-Salt-Added Silica Slurry for the Chemical Mechanical Polishing of the Interlayer Dielectric Film Planarization in ULSI's

Based on the theory of colloid, a new KOH-free silica slurry is developed for chemical mechanical polishing (CMP) to planarize the interlayer dielectric films in ULSI's. The ammonium salt addition to the slurries of pH=6-7 promotes the silica particle agglomeration in the slurry, and enlarges the effective abrasive particle size. The particle agglomeration yields a high polishing rate due to increasing of the mechanical effect, and good particle removability with scrub cleaning is achieved. The ammonium salt-added slurry provides the high-speed CMP without alkaline-metal contamination to the LSI fabrication line.

Fluorinated SiO2 Films For Interlayer Dielectrics In Quarter-Micron Ulsi Multilevel Interconnections

AbstractFluorinated SiO2 films for use as interlayer dielectrics in ULSI multilevel interconnections are investigated. The interlayer dielectric film properties and their formation techniques have to meet the following requirements: (1) a low dielectric constant, (2) a high planarization capability, (3) a high capability for narrow gap filling, and (4) a low deposition temperature for low residual stress. To satisfy these requirements, three technologies have been investigated. They are: (i) a fluorinated SiO2 (SiOF) film by room temperature chemical vapor deposition (RTCVD-SiOF) using fluorotrialkoxysilane (FTAS) and pure water as gas sources, (ii) a room temperature liquid phase deposition (LPD) SiO2 film, and (iii) a fluorinated spin-on-glass (SOG) film by fluorotrialkoxysilane vapor treatment (FAST-SOG). The dielectric constant for SiO2 films can be reduced to 3.7 at 1 MHz by the RTCVD and LPD techniques. Although the FAST and RTCVD techniques cannot achieve full planarization, the LPD technique can achieve both global and local planarization because this technique has high capability for selective SiO2 film deposition. The RTCVD, FAST and LPD techniques have shown the possibility to reduce the film formation temperature to room temperature by catalytic reactions, resulting in low residual stress. Other properties of the RTCVD-SiOF, LPD-SiO2 and FAST-SOG films are good enough for the interlayer dielectric film application. The LPD-SiO2 film shows higher endurance properties to moisture than the RTCVD-SiOF and FAST-SOG films.

Postchemical‐Mechanical Planarization Cleanup Process for Interlayer Dielectric Films

This paper details postchemical‐mechanical planarization cleanup process development for interlayer dielectric films. The scope of the paper includes defining a base line polish process and developing a post‐CMP cleanup process using 150 mm wafers. The efficiency of the cleaning process was evaluated by the number of (≥0.2 μm) particles remaining on the wafer surface. The cleanup strategy included use of wet wafer transfer, postpolish buffing and rinse, basic chemistry, surfactants, HF, megasonics, and double‐sided scrubbers. Postpolish buffing and rinsing were performed on the polisher. The optimized megasonic process used dilute as the cleaning chemistry. To optimize the mechanical work done on the wafer surface during scrubbing, brush rotation speed, wafer rotation speed, brush height (force), and cleaning time were varied on both the scrubbers. Basic chemistry was used only in the OnTrak scrubber. Dilute and DI water were chosen for the optimized OnTrak and Dai Nippon Screen (DNS) processes, respectively. All the HF work was performed on the DNS scrubber. The overall conclusion is that the polisher plays a major role in achieving low particle levels. Postpolish buffing and high pressure DI water spindle rinse at high spindle rotation after polish are critical for particle reduction. Optimized cleaning processes using either of the double‐sided scrubbers or using the batch megasonic cleanup followed by either of the double‐sided scrubbers provided comparable particle performance. HF was effective in the removal of ionic and metallic contaminants, but further investigation is required to check possible improvement in particle performance.

Atomic force microscopy: a key to direct wafer bonding technology

Wafer bonding is the dedicated joining of two semiconductor wafer surfaces without the use of adhesives. Specific applications include silicon-oninsulator (SOI), sensors and actuators, and threedimensional integrated microstructures [1-5]. Although a complete theory has not been presented to explain the bonding process, it is generally accepted that the attractive interfacial force between the two surfaces that are separated only by atomic distances is responsible for the initial bonding. These attractive interracial forces are believed to be either electrostatic or chemical in nature. When the two wafers are contacted a relatively weak adhesive force is developed between the surfaces. This initial bond can be strengthened by additional processing such as thermal annealing. The sum of the attractive chemical or ionic interfacial forces balance against the mechanical forces exerted by surface contaminants, roughness, waviness, and wafer bow to determine if an initial bond will form [6]. It is obvious, therefore, that surface-related defects such as particulate contamination, surface roughness, and surface waviness must be minimized and controlled in order to optimize the initial contact for successful bonding to take place. Due to this fact the development of wafer bonding has been highly focused on smooth films such as thermal oxides and bare silicon surfaces. Chemically vapour deposited (CVD) oxides are widely used for the development of integrated circuit (IC) technologies. These CVD oxides may be good candidates for low-temperature wafer bonded surfaces. Structures that do not have surfaces that naturally bond may still be bonded by using deposited films such as oxides as an intermediate layer. P r e v i o u s l y , Si3N 4 and TiN deposited films have been found to form low-temperature bonds [7, 8]. Two other possibilities for low-temperature bondable deposited films are borophosphosilicate glass (BPSG), and low pressure chemically vapour deposited (LPCVD) undoped SiO2. BPSG is used extensively in microelectronics device fabrication as an interlayer dielectric film due to its excellent planarization, gettering and flow properties [9]; LPCVD SiO2 is used in applications where there are stringent step coverage and gap-filling requirements [10]. The successful and reliable bonding of these films would be a very important milestone in the realization of novel structures such as three-dimensional ICs

Properties of liquid-phase-deposited SiO 2 films for interlayer dielectrics in ultralarge-scale integrated circuit multilevel interconnections

Properties of a new fluorinated SiO 2 film for interlayer dielectrics in multilevel interconnections of ultralarge-scale integrated circuits (ULSIs) are investigated. The fluorinated SiO 2 films are formed at 35 °C by a liquid phase deposition (LPD) technique using a supersaturated hydrofluosilicic acid (H 2SiF 6) aqueous solution. The LPD SiO 2 film surface profiles on polysilicon and aluminum wirings are flat enough, indicating that the LPD technique has good capability for the surface planarization of interlayer dielectric films. The compositions of as-deposited LPD SiO 2 films and those annealed at 400 and 900 °C are SiO 1.85F 0.15, SiO 1.85F 0.15 and SiO 1.90F 0.10 respectively. The LPD SiO 2 film deposition mechanism is explained as follows: (i) fluorosilanols [F n Si(OH) 4− n ] formation; (ii) fluorosilanol oligomer formation by a catalytic reaction in the solution; (iii) oligomer adsorption onto the substrate surface; (iv) oligomer polymerization by a catalytic reaction. The absorption peak position, full width at half-maximum (FWHM) and absorption coefficient for the Si-O bond in the Fourier transform infrared spectra for the as-deposited LPD SiO 2 films are 9.17 micrometer, 0.83 micrometer and 1.19 × 10 6 m -1, respectively, indicating that the films are formed by tightly bonded Si-O networks. The as-deposited LPD SiO 2 films have a refractive index of 1.433, a density of 2.19 × 10 3 kg m -3, an etching rate (measured using 1:30 buffered hydrofluoric acid (HF) solution) of 83 nm min -1, and a residual stress of 20 MPa (tensile). The film shrinkages after annealing at 400 and 900 °C are 0.8% and 2.0% respectively. Although these properties are changed by annealing at 400 and 900 °C, these values are still better than those of SiO 2 films deposited by chemical vapor deposition (CVD) at 400 °C for use as interlayer dielectric films. The LPD SiO 2 films have better electrical properties, such as lower leakage current, higher dielectric breakdown strength (> 6.3 × 10 8 V m -1) and lower dielectric constant (< 3.9 at 1 MHz), than the CVD SiO 2 films.