Process optimization of dielectrics chemical mechanical planarization processes for ultralarge scale integration multilevel metallization

Abstract

The requirements of gap-fill and global planarization for interlayer dielectric films obtain more and more importance as the size of the integrated circuits shrinks. Typical dimensions are 0.35 μm for gaps between 0.7 μm high aluminum interconnect lines with an aspect ratio of 2:1. The push of leading edge ultralarge scale integration manufacturing technologies toward the formation of sub 0.1 μm feature sizes places extreme performance demands on the processes and equipment used. At submicron linewidths, the depth-of-focus was limiting technology and chemical mechanical planarization (CMP) became a necessary tool for feature sizes of 0.35 μm and below. Thus, CMP emerged quickly and has become quite sophisticated [R. DeJule, Semicond. Int. 11, 15 (1996)]. Also, in order to fill the small feature sizes high-density plasma chemical vapor deposition (HDP–CVD) of insulators gained increasing attention in the semiconductor world. Due to the uniform thickness of the HDP intermetal dielectric (see Fig. 1) the polishing time is shortened, pad wear is reduced, and thus, increasing the intervals between pad dressing. An increased throughput, as well as extended CMP stability and repeatability can be achieved. A saving in processing time as compared to standard techniques up to 35% is possible. In this article we describe the major dependencies of machine parameters versus experimental results for different CMP processes.