Distribution Of Interface States Research Articles

Impact of voltage and frequency on electrical characteristics of MIS capacitors with triphenylamine layer

This study examines the effect of triphenylamine (TPA) interlayers on the electrical properties of Al/TPA/p-Si metal-interlayer/insulator material-semiconductor (MIS) capacitors. Using Gaussian software, TPA molecular structure was optimized, and HOMO-LUMO energy levels were simulated. Capacitance-conductance-voltage (C-G-V) measurements were performed at room temperature over −4 V to +4 V and 50 kHz–700 kHz. AFM and SEM analysis showed TPA films were smooth with a uniform thickness of about 178 nm. The C-V characteristics revealed a frequency-dependent decrease in capacitance, indicating a continuous distribution of interface states. Barrier height (ΦB) increased from 0.305 eV at 50 kHz to 0.655 eV at 700 kHz, while the active interface trap density (Dit) decreased from 6.73 × 1012 eV−1 cm−2 to 3.23 × 1011 eV−1 cm−2. Additionally, the accumulating region exhibited low series resistance values (between 6.88 and 8.44 Ω). These results suggest that TPA thin films are effective for MIS capacitors.

Continuous distribution of interface states in n-type double-side poly-Si/SiOx passivating contact solar cells

Advanced passivation contact in high-efficiency silicon solar cells plays an important role for the sake of minimizing recombination losses. A stack of heavily doped polycrystalline silicon (poly-Si) and tunnel SiOx contact has attracted much attention, benefitting from its excellent characteristics of carrier selectivity and passivation, and which has been successfully applied in double-side poly-Si/SiOx passivating contact solar cells. Note that characteristics analysis of defects at tunnel SiOx/c-Si (crystalline silicon) interface remains an issue of concern. Herein, we observe capacitance transient spectroscopy arise from both electron and hole traps in the passivating contact structure of poly-Si(p+)/tunnel SiOx/c-Si(n). Subsequently, we propose a skillful procedure of deep-level transient spectroscopy (DLTS) measurement to confirm that the observed electron and hole traps are located at the tunnel SiOx/c-Si interface but not in the bulk of the c-Si substrate. Finally, we show a clear physical picture of continuous energy distribution for interface states.

Dependence of the Spill Back Effect on the Energy Level Distribution of Interface States Under the Transfer Gate in CMOS Image Sensor

Dependence of the Spill Back Effect on the Energy Level Distribution of Interface States Under the Transfer Gate in CMOS Image Sensor

Barrier Inhomogeneity of Pt/GaN Junctions with a Low-Temperature ALD Grown ZnO Interlayer

Semiconducting GaN can realize high performance electronic and power devices owing to its high electron mobility and thermal conductivity where good metal-semiconductor contact is prerequisite. In this work, using thermal atomic layer deposition (ALD), ZnO interlayer was grown at 80°C on GaN and the Pt/ZnO/GaN heterojunctions were electrically characterized. The analyses on the current–voltage (I–V) and capacitance (C–V) data showed that the forward I–V conduction was involved with the inhomogeneous Schottky barrier. The higher density of interface states from I–V data than that from C–V data was attributed to nonuniform distribution of interface states. In addition, high density of interface states caused localized high electric field, caused higher Poole Frenkel emission coefficients than the theoretical one.

Fabrication of n-Si/n-Ga2O3 heterojunctions by surface-activated bonding and their electrical properties

We studied electrical properties of n-Si/n-Ga2O3 heterojunctions fabricated by surface-activated bonding. The energy barrier heights (qϕb) at the Si/Ga2O3 interface for different reverse voltages (Vrev) were derived from temperature-dependent current density–voltage (J–V–T) characteristics. With shifting Vrev to the negative direction, qϕb gradually decreased and reached a constant value due to negatively charged interface states. The conduction band offset at the heterointerface was estimated to be 0.18 eV from the Vrev dependence of qϕb. The qϕb calculated from a capacitance of the heterojunction at thermal equilibrium was larger than those derived from the J–V–T characteristics, attributing to spatially inhomogeneous qϕb caused by the non-uniform distribution of the charged interface states. The density of shallow interface states was also extracted from the reverse J–V–T characteristics, which was estimated to be about 6 × 1012 cm−2 eV−1.

The Hydrogenation Impact on Electronic Properties of p-Diamond/n-Si Heterojunctions.

The undoped polycrystalline diamond films (PDFs) have been deposited on n-type silicon (Si) by Hot Filament Chemical Vapor Deposition (HF CVD) technique. The reaction gases are a mixture of methane and hydrogen. The obtained PDFs were characterized by scanning electron microscopy (SEM) and Raman spectroscopy which, in addition to the diamond phase, also confirms the presence of sp hybridized carbon bonds. As-grown CVD diamond layers are hydrogen terminated and show p-type conductivity. The effect of the level of hydrogenation on the electrical properties of p-diamond/n-Si heterojunctions has been investigated by temperature dependent current–voltage (J-V/T) characteristics. The obtained results suggest that the energy distribution of interface states at the grain boundary (GB) subjected to hydrogenation becomes shallower, and the hole capture cross-section can be reduced. Hydrogenation can lead to a significant reduction of the GB potential barrier. These results can be interesting from the point of view of hydrogen passivation of GBs in microelectronics.

Detailed Insight into the CZTS/CdS Interface Modification by Air Annealing in Monograin Layer Solar Cells

Relatively fast achievements in the kesterite solar cell technology have been made over the last decade, but the experimental efficiency is still ∼13%. One proposed reason is an inappropriate band alignment with Cu2ZnSnS4 (CZTS) and CdS that results in strong interface recombination losses. Results of this work show that the temperature and duration of air annealing of the CZTS/CdS heterojunction are essential for device performance. Soft annealing slightly improved the device efficiency due to the elemental intermixing at the interface. On the other hand, extended annealing increased absorber band gap energy, resulting in higher VOC values, indicating the improved Cu–Zn ordering in the CZTS structure, which also could be expected to have a beneficial influence on the device performance. However, interface analysis revealed that the CZTS absorber surface layer was Cu-rich, providing the reason for the reduction in CZTS solar cell performance. The effect of annealing on the interface defects was analyzed by the capacitance–frequency–voltage (C–V–f) analysis combined with SCAPS simulations. C–V–f-based loss maps showed that air annealing modifies the density distribution of asymmetrical interface states at the CZTS/CdS interface, which becomes fully symmetrical for longer annealing times at 200 °C.

Interface States in the Acoustic Quasiperiodic System Based on Non‐Bragg Resonances

Bragg resonances have been observed in traditional quasiperiodic waveguides for years. To enhance Bragg resonances and form Bragg gaps with high attenuation, a large number of units have been included. Here, a Fibonacci quasiperiodic acoustic waveguide based on an intense resonance mechanism is proposed to realize non‐Bragg resonances. In a waveguide with fewer units, non‐Bragg resonances can still be excited and create the related non‐Bragg gaps with high attenuation beyond the Bragg ones. Furthermore, an interface state arising in non‐Bragg gaps is experimentally observed by fabricating the mirror‐symmetry structure of Fibonacci quasi‐periodic waveguides. The field distribution of interface states exhibits a significant feature of sound energy, which is localized at a quarter wavelength from the interface of the mirror structures on both sides. Unlike the interface state in Bragg gaps (the localized sound energy distributes along the longitudinal direction), the interface state in non‐Bragg gaps displays localization along the longitudinal and radial directions, and the field distribution is like a dipole, which can be used to optimize traditional quasiperiodic waveguide structures and pave the way for various functional devices, which include multimode filters, sensors, couplers, and so on.

Layout dependent hot-carrier-injection-induced pLDMOS degradation from a non-destructive characterization viewpoint

Vgmax Hot-Carrier-Injection (HCI) degradation in Multi-finger p-Laterally-Diffused Metal-Oxide-Semiconductor Field-Effect-Transistors (LDMOSFET) had been investigated by Multi-Region Direct-Current-Current-Voltage (MR-DCIV) characterization method-probing the interface state distribution along the channel, accumulation and (Shallow Trench Isolation) STI-drift region. The method feasibility was verified by device simulation and stress experiment. The enhanced interface state generation in the channel and accumulation region was clearly revealed in multi-finger layout device. This layout dependent degradation was associated with self-heating effect and temperature accelerated Vgmax HCI stress.

Suppression and characterization of interface states at low-pressure-chemical-vapor-deposited SiNx/III-nitride heterostructures

Silicon nitride (SiNx) grown by low-pressure chemical vapor deposition (LPCVD) at a reduced growth temperature (650 °C), is utilized for fabrication of GaN metal–insulator-semiconductor (MIS) power devices. An atomically sharp interface between the LPCVD-SiNx and GaN was achieved, featuring a disordered region with only a thickness of 2.5 ~ 5 Å. A fabricated LPCVD-SiNx/GaN/AlGaN/GaN MIS diode exhibits a sharp two-step capacitance–voltage behavior with small frequency dispersion of 0.4 V in the right step. The improved interface was quantified by a well-elaborated constant-capacitance deep-level transient Fourier spectroscopy (CC-DLTFS), delivering quite low density of 1.5×1013cm-2 eV-1 at the level depth of 30 meV and about 4×1011~1.2×1012cm-2eV-1 at the level depth of 1 eV. Distributions of interface states can be described by a proposed physics-based decoupling function featuring an exponential law. A discrete level at the SiNx/GaN border or in the barrier layer with the level depth and the capture cross section being 0.8 eV and 5.5×10-14cm2 respectively, can thus be detached from the interface states.

Refined analysis of C–V and I–V characteristics of Al/dielectric/Si structures containing nanosized Ta2O5/SiOxNy dielectric stack

In this work we carry out a refined analysis of the C–V and I–V characteristics of Al/Ta2O5/SiOxNy/Si structures at limited voltages (from −3.0 V to +1.0 V). The modified Terman method was used to determine the interface state densities over the silicon bandgap, and an extended comprehensive model was utilised to determine the I–V characteristics of metal/high-κ/SiO2/Si structures.A sharp peak in interface states distribution is observed at around 0.1 eV above the valence band top; its presence is identified as the origin of the double-knee shaped C–V characteristics. The substantial contribution of the Schottky effect was observed in the leakage currents at low voltages.

Energy distribution of interface states generated by oxygen plasma treatment for control of threshold voltage in pentacene thin-film transistors

Pentacene metal-oxide-semiconductor (MOS) capacitors with a SiO2 dielectric treated by oxygen plasma have been studied by capacitance-voltage (C-V) measurements to investigate the energy distribution of the interface states. Oxygen plasma treatment, which is used for control of the threshold voltage in pentacene thin-film transistors, shifted the C-V curves of pentacene MOS capacitors to a positive gate voltage as well as the transfer curves of pentacene thin-film transistors (TFTs). The shift is explained by electrons captured at interface states generated by oxygen plasma treatment. The interface states capturing the electrons are expected to locate at low energy levels. The energy distribution of the interface states locating at middle or high energy levels was extracted by a method equivalent to the Terman method. By use of the method in two steps, the interface state densities distributed at middle and high energy levels (D M and D H) were separately obtained. D M and D H were of the order of 1010–1012 cm−2 eV−1, and increased with an increase in plasma treatment time.

Negative resistance, capacitance in Mn/SiO2/p-Si MOS structure

In this work is that we have manufactured a new structure that had not been studied by researchers before. This structure is Mn/SiO2/Si was synthesised by liquid phase epitaxy (LPE) as a metal-oxide- semiconductor (MOS) and can be used as a tunneling diode; demonstrated from I–V measurement and negative resistance. The structure and its characterization were examined by scanning electron microscope, XRD diffraction, C-V and I–V measurements. We studied the temperature, voltage dependence of dielectric and electrical parameters of the fabricated Mn/SiO2/P-Si MOS device. I–V measurements for this structure display diode tunnel behavior with negative resistance. Parameters such as series resistance (Rs), permittivity (ε′), dielectric loss (ε″), a tangent of the dielectric loss factor (tan δ), real and imaginary parts of electrical modulus (M′ and M″) and ac conductivity were examined in a temperature range of 303–393 K and frequency range (10 Hz–20 MHz) under 1 Vrms applied voltage along with dc bias range of (−2.0–2.0 V). We found that thermal reordering of the interface is a reason for a continuous density distribution of interface states with homogenous relaxation time, which in turn induced a higher sensitivity to both C and G/w response with electric field frequency. The device showed negative values for capacitance (C), dielectric loss (ε″), and dielectric loss tangent (tan δ) at all temperatures.

Effects of Charge Trapping at the MoS2–SiO2 Interface on the Stability of Subthreshold Swing of MoS2 Field Effect Transistors

The stability of the subthreshold swing (SS) is quite important for switch and memory applications in logic circuits. The SS in our MoS2 field effect transistor (FET) is enlarged when the gate voltage sweep range expands towards the negative direction. This is quite different from other reported MoS2 FETs whose SS is almost constant while varying gate voltage sweep range. This anomalous SS enlargement can be attributed to interface states at the MoS2–SiO2 interface. Moreover, a deviation of SS from its linear relationship with temperature is found. We relate this deviation to two main reasons, the energetic distribution of interface states and Fermi level shift originated from the thermal activation. Our study may be helpful for the future modification of the MoS2 FET that is applied in the low power consumption devices and circuits.

Investigation of the electrical properties of diodes by crosschecking dependence on the presence of (nanocarbon-PVP) interface layer

The Al/p-Si (metal-semiconductor (MS)) and Al/nanocarbon-PVP/p-Si (metal-polymer-semiconductor) type Schottky barrier diodes (SBDs) were fabricated in same conditions to determine the existence of an increase in the performance of Al/p-Si diode and they were called as D1 and D2, respectively. For this purpose, the electrical properties of the diodes were investigated using the current–voltage and impedance–voltage measurements in wide bias voltage. The ideality factor, reverse-saturation current and zero-bias barrier height values were calculated from the linear part of the forward bias lnI–V plot as 6.23, 2.35 ✕ 10–8A, 0.68 eV for D1 and 2.86, 4.27 ✕ 10–9A, 0.73 eV for D2, respectively. It is seen from results that the value of rectifier rate for D2 is about 8 times higher than for D1. The values of barrier height, Fermi energy level, the number of doped acceptor atoms and depletion layer width were obtained. The values of series resistance and special density distribution of interface states’ values also considerably decrease using (nanocarbon Polyvinylpyrrolidone (PVP)) interlayer. All these results confirmed that the nanocarbon-PVP polymer interlayer leads to a seriously increase in the performance of the MS diodes and hence it can be successfully used as an insulator in view of low cost, grown by simple methods.

AC electrical properties of Schottky diode based on nanocrystalline silicon thin films

Thin film of hydrogenated amorphous silicon has been deposited with plasma enhanced chemical vapor deposition technique. The obtained samples were thermally annealed at 700°C and 900°C to get nanocrystalline silicon. The energy band gap has been determined using the Tauc's model for indirect transitions. The band gap of the layer increases from 1.75eV to 2.1 eV as the annealing temperature increases and indicates a structure change from amorphous to nanocrystalline phase. The electrical characterization of the Au/nc-Si:H Schottky diodes was performed using conductance-voltage-frequency (G/ω-V) and capacitance-voltage (C–V) measurements. The presence of a peak in C–V characteristic and the increase of capacitance with decreasing frequency is a signature of a continuous distribution of interface states. According to characteristic analysis, the amorphous region and nanocrystalline phase dominated over distinguishable frequency scales. The response of the former one emerges at low frequencies whereas the other stands out at extremely high frequencies.

Electrical properties of Al/PCBM:ZnO/p-Si heterojunction for photodiode application

In this paper, the electrical characteristics of spin-coated PCBM:ZnO interlayered Al/PCBM:ZnO/Si diode are investigated under the aim of photodiode application. Under dark condition, the diode shows about four orders in magnitude rectification rate and diode illumination results in efficient rectification with increase in intensity. The analysis of current-voltage curve results a non-ideal diode characteristics according to the thermionic emission model due to the existence of parasitic resistances and interface states. The measured current-voltage values are used to extract the barrier height and ideality factor under dark and illumination conditions. Under illumination, photo-generated carriers contribute to the current flow and linear photo-conductivity behavior in photo-current measurements with illumination shows the possible use of hybrid PCBM:ZnO layer in Si-based photodiodes. In addition, change in the series and shunt resistance values under illumination is found to be effective in this light-sensing behavior of the diode. This characteristic is also observed from the typical on/off illumination switching behavior for the photodiodes in transient photo-current, photo-capacitance and photo-conductance measurements with the quick response to the illumination. The deviations from ideality are also discussed by means of distribution of interface states and series resistance depending on the applied frequency and bias voltage.

A Temperature Sensor Based on Al/p-Si/CuCdO2/Al Diode for Low Temperature Applications

CuCdO2 delafossite oxide film as an interface layer was coated by sol–gel spin coating on p-Si substrate, and thus an Al/p-Si/CuCdO2/Al diode was fabricated. Scanning electron microscopy (SEM) with energy dispersive spectroscopy (EDS) was used to obtain an image of the CuCdO2 oxide film. The temperature-dependent behavior of the diode was studied by current–voltage (I–V) and capacitance/conductance–voltage (C/G–V) measurements over the 100–400 K temperature range. It is observed that the ideality factor (n) decreases and zero-bias barrier height (Φb0) increases with an increase in temperature. This abnormal behavior of n and Φb0 is attributed to barrier inhomogeneities by assuming Gaussian distribution (GD) at the metal–semiconductor interface. For each temperature, the barrier height values obtained from both the conventional I–V and Norde method show good agreement with each other. The I–V–T characteristics have shown the GD, giving a mean barrier height ($$ {\bar{\Phi }}_{b0} $$) of 1.04 eV and a standard deviation (σs) of 0.12 V. A modified Richardson plot of [ln(I0/T2) − q2σs2/2k2T2 versus q/kT] yields $$ {\bar{\Phi }}_{b0} $$ and A* as 1.06 eV and 31.21 A cm−2 K−2 (indicating an agreement with the theoretical value of 32 A cm−2 K−2), showing the promise of CuCdO2/Si as temperature sensing with a Schottky junction. In addition, C–V and G–V measurements show that the C value decreases and the G value increases as the frequency increases, depending on a continuous distribution of interface states. Also, the capacitance and the conductance values decrease with increasing temperature. The results suggest that Al/p-Si/CuCdO2/Al diode can be used for temperature sensing applications.

Analyzed electrical performance and induced interface passivation of fabricated Al/NTCDA/p-Si MIS–Schottky heterojunction

In this research, the significant role of 1,4,5,8-naphthalenetetracarboxylic-dianhydride, NTCDA, thin film on the Al/p-Si barrier under different temperatures is investigated. The structural and topographical properties of the thermally evaporated NTCDA thin film are investigated using a transmission electron microscope, TEM, and atomic force microscope, AFM, respectively, and elucidated that the fabricated films have a smooth nanocrystalline nature with an average crystallite size about 89 nm and average roughness about 3.15 nm. Furthermore, the current–voltage (I–V) characteristics of Al/NTCDA/p-Si/Al device are studied under dark conditions at different temperatures (313–383 K). The Schottky diode electronic parameters such as ideality factor, n, barrier height, ΦB, and reverse saturation current, Is, are calculated at each temperature. A clear increment of ΦB from 0.74 to 0.88 eV accompanied by a clear decrement of n values from 5.83 to 4.99 under increasing temperature (313–383) K is noticed. Due to the inhomogeneity of barrier height, the Gaussian distribution of Schottky barrier height is employed to estimate the mean value of barrier height and standard deviation and found to be 1.5 eV and 20 mV, respectively. The modified Richardson plot is used to estimate the modified Richardson constant and found to be 35.2 A cm−2 K−2 which is close to the known value of p-Si. Moreover, the conduction mechanism in forward and reverse biasing is explained in details. The modified Norde's function is employed for estimating the series resistance, Rs, and barrier height of the fabricated device at each temperature, where the values of Rs showed a decrement behavior from 3.564 to 1.165 kΩ upon increasing the temperature. The process of inserting NTCDA between electrode and p-Si influenced the distribution of interface states for MIS Schottky diode at different temperatures and is explained as a passivation process of the device's interface states.

Effect of measurement frequency on admittance characteristics in Al/p-Si structures with interfacial native oxide layer

Al/p-Si/Al diodes with interfacial native oxide layer were formed. Their frequency induced admittance-voltage measurements were made. The frequency-dependent density distribution of interface states has been determined from the corrected characteristics by considering the series resistance effect which masks the interface trap loss. The majority carrier density corresponding to the depletion and inversion parts of the C-2-V curve, was determined 1.82 x 1014 and 4.48 x 1014 cm-3 at 1000 kHz, respectively. The fact that the carrier density obtained from the inversion part of the plot is higher than that obtained from the depletion part can be related to the increase in the density of negative space charge in the depletion region.The value of was determined as 0.95 eV from the same plot. Interface state density decreased from 4.31 x 1012 eV-1cm-2 at 100 kHz to 7.30 x 1011 eV-1 cm-2 at 1000 kHz, because the interface charges do not follow the ac signal and do not contribute to capacitance values in high frequencies.